Datasheet
Table Of Contents
- 1. General description
- 2. Features and benefits
- 3. Applications
- 4. Ordering information
- 5. Block diagram
- 6. Pinning information
- 7. Functional description
- 7.1 ARM Cortex-M0 processor
- 7.2 On-chip flash program memory
- 7.3 On-chip SRAM
- 7.4 Memory map
- 7.5 Nested Vectored Interrupt Controller (NVIC)
- 7.6 IOCONFIG block
- 7.7 Fast general purpose parallel I/O
- 7.8 UART
- 7.9 SPI serial I/O controller
- 7.10 I2C-bus serial I/O controller
- 7.11 C_CAN controller
- 7.12 10-bit ADC
- 7.13 General purpose external event counter/timers
- 7.14 System tick timer
- 7.15 Watchdog timer
- 7.16 Clocking and power control
- 7.17 System control
- 7.18 Emulation and debugging
- 8. Limiting values
- 9. Static characteristics
- 10. Dynamic characteristics
- 11. Application information
- 12. Package outline
- 13. Soldering
- 14. Abbreviations
- 15. Revision history
- 16. Legal information
- 17. Contact information
- 18. Contents

LPC11CX2_CX4 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3.1 — 15 May 2013 14 of 62
NXP Semiconductors
LPC11Cx2/Cx4
32-bit ARM Cortex-M0 microcontroller
[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled (pins pulled up to full V
DD
level); IA = inactive,
no pull-up/down enabled.
[2] 5 V tolerant pad. RESET
functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up
from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 26
for the
reset pad configuration.
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 25
).
[4] I
2
C-bus pads compliant with the I
2
C-bus specification for I
2
C standard mode and I
2
C Fast-mode Plus.
[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 25
).
[6] 5 V tolerant digital I/O pad without pull-up/pull-down resistors.
[7] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
GND 21 - - - Ground for CAN transceiver.
V
DD
8; 44 - I - Supply voltage to the internal regulator, the external rail, and the
ADC. Also used as the ADC reference voltage.
XTALIN 6
[7]
- I - Input to the oscillator circuit and internal clock generator circuits.
Input voltage must not exceed 1.8 V.
XTALOUT 7
[7]
- O - Output from the oscillator amplifier.
V
SS
5; 41 - I - Ground.
Table 4. LPC11C22/C24 pin description table
Symbol Pin Start
logic
inputs
Type Reset
state
[1]
Description