Datasheet

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Table Of Contents

1. General description

The LPC11Cx2/Cx4 are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed

for 8/16-bit microcontroller applications, offering performance, low power, simple

instruction set and memory addressing together with reduced code size compared to

existing 8/16-bit architectures.

The LPC11Cx2/Cx4 operate at CPU frequencies of up to 50 MHz.

The peripheral complement of the LPC11Cx2/Cx4 includes 16/32 kB of flash memory,

8 kB of data memory, one C_CAN controller, one Fast-mode Plus I

C-bus interface, one

RS-485/EIA-485 UART, two SPI interfaces with SSP features, four general purpose

counter/timers, a 10-bit ADC, and up to 40 general purpose I/O pins.

On-chip C_CAN drivers and flash In-System Programming tools via C_CAN are included.

In addition, the LPC11C22 and LPC11C24 parts include an on-chip, high-speed CAN

transceiver.

2. Features and benefits

 System:

 ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.

 ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).

 Serial Wire Debug.

 System tick timer.

 Memory:

 32 kB (LPC11Cx4) or 16 kB (LPC11Cx2) on-chip flash program memory.

 8 kB SRAM data memory.

 In-System Programming (ISP) and In-Application Programming (IAP) via on-chip

bootloader software.

 Flash ISP commands can be issued via UART or C_CAN.

 Digital peripherals:

 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors.

 40 GPIO pins on the LPC11C12/C14 parts; 36 GPIO pins on the LPC11C22/C24

parts.

 GPIO pins can be used as edge and level sensitive interrupt sources.

 High-current output driver (20 mA) on one pin.

 High-current sink drivers (20 mA) on two I

C-bus pins in Fast-mode Plus.

 Four general purpose counter/timers with a total of four capture inputs and 13

(LPC11C12/C14) or 12 (LPC11C22/C24) match outputs.

LPC11Cx2/Cx4

32-bit ARM Cortex-M0 microcontroller; 16/32 kB flash, 8 kB

SRAM; C_CAN

Rev. 3.1 — 15 May 2013 Product data sheet

Summary of content (62 pages)

PAGE 1
LPC11Cx2/Cx4 32-bit ARM Cortex-M0 microcontroller; 16/32 kB flash, 8 kB SRAM; C_CAN Rev. 3.1 — 15 May 2013 Product data sheet 1. General description The LPC11Cx2/Cx4 are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for 8/16-bit microcontroller applications, offering performance, low power, simple instruction set and memory addressing together with reduced code size compared to existing 8/16-bit architectures. The LPC11Cx2/Cx4 operate at CPU frequencies of up to 50 MHz.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller         Programmable WatchDog Timer (WDT). Analog peripherals:  10-bit ADC with input multiplexing among 8 pins. Serial interfaces:  UART with fractional baud rate generation, internal FIFO, and RS-485 support.  Two SPI controllers with SSP features and with FIFO and multi-protocol capabilities.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC11C12FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.4 mm LPC11C14FBD48/301 LQFP48 LQFP48: plastic low profile quad flat package; 48 leads; body 7  7  SOT313-2 1.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 5.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 6. Pinning information 37 PIO3_1/DSR 38 PIO2_3/RI/MOSI1 39 SWDIO/PIO1_3/AD4/CT32B1_MAT2 40 PIO1_4/AD5/CT32B1_MAT3/WAKEUP 41 VSS 42 PIO1_11/AD7 43 PIO3_2/DCD 44 VDD 45 PIO1_5/RTS/CT32B0_CAP0 46 PIO1_6/RXD/CT32B0_MAT0 47 PIO1_7/TXD/CT32B0_MAT1 48 PIO3_3/RI 6.
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LPC11Cx2/Cx4 NXP Semiconductors 37 PIO3_1/DSR 38 PIO2_3/RI/MOSI1 39 SWDIO/PIO1_3/AD4/CT32B1_MAT2 40 PIO1_4/AD5/CT32B1_MAT3/WAKEUP 41 VSS 42 PIO1_11/AD7 43 PIO3_2/DCD 44 VDD 45 PIO1_5/RTS/CT32B0_CAP0 46 PIO1_6/RXD/CT32B0_MAT0 47 PIO1_7/TXD/CT32B0_MAT1 48 PIO3_3/RI 32-bit ARM Cortex-M0 microcontroller PIO2_6 1 36 PIO3_0/DTR PIO2_0/DTR/SSEL1 2 35 R/PIO1_2/AD3/CT32B1_MAT1 RESET/PIO0_0 3 34 R/PIO1_1/AD2/CT32B1_MAT0 PIO0_1/CLKOUT/CT32B0_MAT2 4 33 R/PIO1_0/AD1/CT32B1_CAP0 VSS 5 32 R/PI
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 6.2 Pin description Table 3. LPC11C12/C14 pin description table Symbol Pin Start Type logic inputs Reset Description state [1] PIO0_0 to PIO0_11 RESET/PIO0_0 PIO0_1/CLKOUT/ CT32B0_MAT2 Port 0 — Port 0 is a 12-bit I/O port with individual direction and function controls for each bit. The operation of port 0 pins depends on the function selected through the IOCONFIG register block.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 3. LPC11C12/C14 pin description table Symbol R/PIO0_11/ AD0/ CT32B0_MAT3 Pin 32[5] Start Type logic inputs Reset Description state yes - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO0_11 — General purpose digital input/output pin. I - AD0 — A/D converter, input 0. O - CT32B0_MAT3 — Match output 3 for 32-bit timer 0.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 3. LPC11C12/C14 pin description table Symbol PIO1_7/TXD/ CT32B0_MAT1 Pin 47[3] PIO1_8/ CT16B1_CAP0 9[3] PIO1_9/ CT16B1_MAT0 17[3] PIO1_10/AD6/ CT16B1_MAT1 30[5] PIO1_11/AD7 42[5] Start Type logic inputs Reset Description state no I/O I; PU PIO1_7 — General purpose digital input/output pin. O - TXD — Transmitter output for UART. O - CT32B0_MAT1 — Match output 1 for 32-bit timer 0.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 3. LPC11C12/C14 pin description table Symbol Pin Start Type logic inputs Reset Description state I; PU PIO3_0 — General purpose digital input/output pin. O - DTR — Data Terminal Ready output for UART. I/O I; PU PIO3_1 — General purpose digital input/output pin. I - DSR — Data Set Ready input for UART. I/O I; PU PIO3_2 — General purpose digital input/output pin.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 4.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 4. LPC11C22/C24 pin description table Symbol R/PIO1_0/AD1/ CT32B1_CAP0 R/PIO1_1/AD2/ CT32B1_MAT0 R/PIO1_2/AD3/ CT32B1_MAT1 SWDIO/PIO1_3/ AD4/ CT32B1_MAT2 PIO1_4/AD5/ CT32B1_MAT3/ WAKEUP Pin 33[5] 34[5] 35[5] 39[5] 40[5] Start Type logic inputs Reset Description state yes - I; PU R — Reserved. Configure for an alternate function in the IOCONFIG block. I/O - PIO1_0 — General purpose digital input/output pin.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 4. LPC11C22/C24 pin description table Symbol PIO1_11/AD7 Pin 42[5] Start Type logic inputs Reset Description state no I/O I; PU I - [1] PIO1_11 — General purpose digital input/output pin. AD7 — A/D converter, input 7. PIO2_0 to PIO2_11 Port 2 — Port 2 is a 12-bit I/O port with individual direction and function controls for each bit.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 4. LPC11C22/C24 pin description table Symbol Pin Start Type logic inputs Reset Description state [1] GND 21 - - - Ground for CAN transceiver. VDD 8; 44 - I - Supply voltage to the internal regulator, the external rail, and the ADC. Also used as the ADC reference voltage. XTALIN 6[7] - I - Input to the oscillator circuit and internal clock generator circuits. Input voltage must not exceed 1.8 V.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7. Functional description 7.1 ARM Cortex-M0 processor The ARM Cortex-M0 is a general purpose, 32-bit microprocessor, which offers high performance and very low power consumption. 7.2 On-chip flash program memory The LPC11Cx2/Cx4 contain 32 kB (LPC11C14/C24) or 16 kB (LPC11C12/C22) of on-chip flash program memory. 7.3 On-chip SRAM The LPC11Cx2/Cx4 contain a total of 8 kB on-chip static RAM data memory. 7.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller AHB peripherals LPC11Cx2/Cx4 4 GB 0x5020 0000 0xFFFF FFFF reserved 0xE010 0000 private peripheral bus 16 - 127 reserved 0xE000 0000 0x5004 0000 reserved AHB peripherals 12-15 GPIO PIO3 0x5020 0000 8-11 GPIO PIO2 0x5000 0000 4-7 GPIO PIO1 0-3 GPIO PIO0 APB peripherals reserved 0x5003 0000 0x5002 0000 0x5001 0000 0x5000 0000 0x4008 0000 23 - 31 reserved 0x4005 C000 APB peripherals 1 GB 0x4008 0000 22 SPI1 0x4000
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • Four programmable interrupt priority levels, with hardware priority level masking. • Software interrupt generation. 7.5.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.8 UART The LPC11Cx2/Cx4 contain one UART. Support for RS-485/9-bit mode allows both software address detection and automatic address detection using 9-bit mode. The UART includes a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.8.1 Features • • • • • Maximum UART data bit rate of 3.125 Mbit/s. 16 Byte Receive and Transmit FIFOs.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller The I2C-bus is bidirectional for inter-IC control using only two wires: a Serial CLock line (SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory).
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller • The C_CAN API includes the following functions: – C_CAN set-up and initialization – C_CAN send and receive messages – C_CAN status – CANopen object dictionary – CANopen SDO expedited communication – CANopen SDO segmented communication primitives – CANopen SDO fall-back handler • Flash ISP programming via C_CAN supported. 7.11.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.11.2.6 Time-out function A ‘TXD dominant time-out’ timer is started when the CAN_TXD signal of the C_CAN controller is set LOW. If the LOW state on the CAN_TXD signal persists for longer than tto(dom)TXD, the transmitter is disabled, releasing the bus lines to recessive state.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller – Toggle on match. – Do nothing on match. 7.14 System tick timer The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate a dedicated SYSTICK exception at a fixed time interval (typically 10 ms). 7.15 Watchdog timer The purpose of the watchdog is to reset the microcontroller within a selectable time period. 7.15.1 Features • Internally resets chip if not periodically reloaded. • Debug mode.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller SYSTEM CLOCK DIVIDER AHB clock 0 (system) system clock 18 AHB clocks 1 to 18 (memories and peripherals) SYSAHBCLKCTRL[1:18] (AHB clock enable) IRC oscillator SPI0 PERIPHERAL CLOCK DIVIDER SPI0 UART PERIPHERAL CLOCK DIVIDER UART SPI1 PERIPHERAL CLOCK DIVIDER SPI1 WDT CLOCK DIVIDER WDT main clock watchdog oscillator MAINCLKSEL (main clock select) IRC oscillator SYSTEM PLL system oscillator IRC oscillator SYSPLLCLKSEL (s
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.16.1.3 Watchdog oscillator The watchdog oscillator can be used as a clock source that directly drives the CPU, the watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and temperature is 40 % (see Table 15). 7.16.2 System PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 7.16.5.2 Deep-sleep mode In Deep-sleep mode, the chip is in Sleep mode, and in addition all analog blocks are shut down. As an exception, the user has the option to keep the watchdog oscillator and the BOD circuit running for self-timed wake-up and BOD protection. Deep-sleep mode allows for additional power savings.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. Four additional threshold levels can be selected to cause a forced reset of the chip. 7.17.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller The C_CAN ISP command handler uses the CANopen protocol and data organization method. C_CAN ISP commands have the same functionality as UART ISP commands. 7.17.6 APB interface The APB peripherals are located on one APB bus. 7.17.7 AHBLite The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main static RAM, and the Boot ROM. 7.17.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9. Static characteristics Table 6. Static characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VDD supply voltage (core and external rail) on pins VDD 1.8 3.3 3.6 V IDD supply current Active mode; code - 3 - mA - 9 - mA - 2 - mA - 6 - A - 220 - nA while(1){} executed from flash system clock = 12 MHz VDD = 3.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 6. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IOH HIGH-level output current VOH = VDD  0.4 V; 4 - - mA 3 - - mA 4 - - mA 2.0 V  VDD  3.6 V 1.8 V  VDD < 2.0 V IOL LOW-level output current VOL = 0.4 V 2.0 V  VDD  3.6 V 1.8 V  VDD < 2.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 6. Static characteristics …continued Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IOL LOW-level output current VOL = 0.4 V 4 - - mA 3 - - mA - - 50 mA 2.0 V  VDD  3.6 V 1.8 V  VDD < 2.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller [13] 3-state outputs go into 3-state mode in Deep power-down mode. [14] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [15] To VSS. 9.1 ADC characteristics Table 7. ADC static characteristics Tamb = 40 C to +85 C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller offset error EO gain error EG 1023 1022 1021 1020 1019 1018 (2) 7 code out (1) 6 5 (5) 4 (4) 3 (3) 2 1 LSB (ideal) 1 0 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 VIA (LSBideal) offset error EO 1 LSB = VDD − VSS 1024 002aaf426 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)).
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9.2 C_CAN on-chip, high-speed transceiver characteristics Table 8. Static characteristics Tamb = 40 C to +85 C; VCC = 4.5 V to 5.5 V; RL = 60 ; unless otherwise specified; all voltages are defined with respect to ground; positive currents flow into the IC. Also see Figure 28. Symbol Parameter Conditions Min Typ Max Unit 4.5 - 5.5 V 0.1 1 2.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 8. Static characteristics …continued Tamb = 40 C to +85 C; VCC = 4.5 V to 5.5 V; RL = 60 ; unless otherwise specified; all voltages are defined with respect to ground; positive currents flow into the IC. Also see Figure 28.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9.3 BOD static characteristics Table 10. BOD static characteristics[1] Tamb = 25 C. Symbol Parameter Conditions Vth threshold voltage interrupt level 1 Min Typ Max Unit assertion - 2.22 - V de-assertion - 2.35 - V assertion - 2.52 - V de-assertion - 2.66 - V assertion - 2.80 - V de-assertion - 2.90 - V assertion - 1.46 - V de-assertion - 1.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aaf390 12 IDD (mA) 48 MHz(2) 8 36 MHz(2) 24 MHz(2) 4 12 MHz(1) 0 1.8 2.4 3.0 3.6 VDD (V) Conditions: Tamb = 25 C; active mode entered executing code while(1){} from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; pin CAN_RXD pulled LOW externally.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aaf392 8 IDD (mA) 48 MHz(2) 6 36 MHz(2) 4 24 MHz(2) 12 MHz(1) 2 0 −40 −15 10 35 60 85 temperature (°C) Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the SYSAHBCLKCTRL register (SYSAHBCLKCTRL = 0x1F); all peripheral clocks disabled; internal pull-up resistors disabled; BOD disabled; pin CAN_RXD pulled LOW externally. (1) System oscillator and system PLL disabled; IRC enabled.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aaf457 0.8 IDD (μA) 0.6 VDD = 3.6 V 3.3 V 2.0 V 1.8 V 0.4 0.2 0 −40 −15 10 35 60 85 temperature (°C) Fig 11. Deep power-down mode: Typical supply current IDD versus temperature for different supply voltages VDD LPC11CX2_CX4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 15 May 2013 © NXP B.V. 2013. All rights reserved.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9.5 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both registers and no code is executed. Measured on a typical sample at Tamb = 25 C.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 9.6 Electrical pin characteristics 002aae990 3.6 VOH (V) T = 85 °C 25 °C −40 °C 3.2 2.8 2.4 2 0 10 20 30 40 50 60 IOH (mA) Conditions: VDD = 3.3 V; on pin PIO0_7. Fig 12. High-drive output: Typical HIGH-level output voltage VOH versus HIGH-level output current IOH. 002aaf019 60 T = 85 °C 25 °C −40 °C IOL (mA) 40 20 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5. Fig 13.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aae991 15 IOL (mA) T = 85 °C 25 °C −40 °C 10 5 0 0 0.2 0.4 0.6 VOL (V) Conditions: VDD = 3.3 V; standard port pins and PIO0_7. Fig 14. Typical LOW-level output current IOL versus LOW-level output voltage VOL 002aae992 3.6 VOH (V) T = 85 °C 25 °C −40 °C 3.2 2.8 2.4 2 0 8 16 24 IOH (mA) Conditions: VDD = 3.3 V; standard port pins. Fig 15.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 002aae988 10 Ipu (μA) −10 −30 T = 85 °C 25 °C −40 °C −50 −70 0 1 2 3 4 5 VI (V) Conditions: VDD = 3.3 V; standard port pins. Fig 16. Typical pull-up current Ipu versus input voltage VI 002aae989 80 T = 85 °C 25 °C −40 °C Ipd (μA) 60 40 20 0 0 1 2 3 4 5 VI (V) Conditions: VDD = 3.3 V; standard port pins. Fig 17.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10. Dynamic characteristics 10.1 Flash memory Table 12. Flash characteristics Tamb = 40 C to +85 C, unless otherwise specified. Symbol Parameter Conditions Min [1] Nendu endurance tret retention time ter erase time tprog programming time Typ Max Unit 10000 100000 - cycles powered 10 - - years unpowered 20 - - years sector or multiple consecutive sectors 95 100 105 ms 0.95 1 1.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.3 Internal oscillators Table 14. Dynamic characteristic: internal oscillators Tamb = 40 C to +85 C; 2.7 V  VDD  3.6 V.[1] Symbol Parameter Conditions fosc(RC) internal RC oscillator frequency - Min Typ[2] Max Unit 11.88 12 12.12 MHz [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 10.4 I/O pins Table 16. Dynamic characteristic: I/O pins[1] Tamb = 40 C to +85 C; 3.0 V  VDD  3.6 V. Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3.0 - 5.0 ns tf fall time pin configured as output 2.5 - 5.0 ns [1] Applies to standard port pins and RESET pin. 10.5 I2C-bus Table 17. Dynamic characteristic: I2C-bus pins[1] Tamb = 40 C to +85 C.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller [6] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf. [7] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Table 18.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Tcy(clk) tclk(H) tclk(L) tDS tDH SCK (CPOL = 0) SCK (CPOL = 1) MOSI DATA VALID DATA VALID tv(Q) MISO th(Q) DATA VALID tDS MOSI DATA VALID tDH DATA VALID tv(Q) MISO DATA VALID CPHA = 1 DATA VALID th(Q) CPHA = 0 DATA VALID 002aae830 Pin names SCK, MISO, and MOSI refer to pins for both SPI peripherals, SPI0 and SPI1. Fig 22.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11. Application information 11.1 ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in Table 7: • The ADC input trace must be short and as close as possible to the LPC11Cx2/Cx4 chip. • The ADC input traces must be shielded from fast switching digital signals and noisy power supply lines.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller LPC1xxx L XTALIN XTALOUT = CL CP XTAL RS CX2 CX1 002aaf424 Fig 24. Oscillator modes and models: oscillation mode of operation and external crystal model used for CX1/CX2 evaluation Table 19.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller accordingly to the increase in parasitics of the PCB layout. 11.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11.5 Reset pad configuration VDD VDD VDD Rpu reset ESD 20 ns RC GLITCH FILTER PIN ESD VSS 002aaf274 Fig 26. Reset pad configuration 11.6 C_CAN with external transceiver (LPC11C12/C14 only) BAT 3V 5V VIO VCC CANH CANH S TJF1051 TXD RXD CANL CANL GND LPC11C12/C14 PIOx_y CAN_TXD CAN_RXD 002aaf911 Fig 27.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 11.7 C_CAN with on-chip, high-speed transceiver (LPC11C22/C24 only) VDD 3V 5V VDD_CAN VCC VDD LPC11C22/C24 CANH CAN_TXD CANH CAN HIGH-SPEED TRANSCEIVER CANL C_CAN CAN_RXD CANL STD GND 002aaf910 Fig 28. Connecting the CAN high-speed transceiver to the CAN bus (LPC11C22/C24) LPC11CX2_CX4 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3.1 — 15 May 2013 © NXP B.V. 2013.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 12. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2 c y X 36 25 A 37 24 ZE e E HE A A2 (A 3) A1 w M θ bp pin 1 index Lp L 13 48 detail X 12 1 ZD e v M A w M bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp v w y mm 1.6 0.20 0.05 1.45 1.35 0.25 0.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 13. Soldering Footprint information for reflow soldering of LQFP48 package SOT313-2 Hx Gx P2 Hy (0.125) P1 Gy By Ay C D2 (8×) D1 Bx Ax Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 0.500 0.560 Ax Ay 10.350 10.350 Bx By C D1 D2 Gx 7.350 7.350 1.500 0.280 0.500 7.500 Gy Hx Hy 7.500 10.650 10.650 sot313-2_fr Fig 30.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 14. Abbreviations Table 21.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 15. Revision history Table 22. Revision history Document ID Release date Data sheet status Change notice Supersedes LPC11CX2_CX4 v.3.1 20130515 Product data sheet - LPC11CX2_CX4 v.3 Modifications: • • Table 3 and Table 4: Added “5 V tolerant pad” to RESET/PIO0_0 table note. Table 5: – Added Table note 2. – Corrected VDD min and max. • • LPC11CX2_CX4 v.3 Modifications: LPC11CX2_CX4 v.2 Modifications: LPC11C12_C14 v.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
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LPC11Cx2/Cx4 NXP Semiconductors 32-bit ARM Cortex-M0 microcontroller 14 15 16 16.1 16.2 16.3 16.4 17 18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . . Legal information. . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. .