Datasheet

LPC111X All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 9.2 — 26 March 2014 58 of 127
NXP Semiconductors
LPC1110/11/12/13/14/15
32-bit ARM Cortex-M0 microcontroller
8. Limiting values
[1] The following applies to the limiting values:
a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive
static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated
maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V
SS
unless
otherwise noted.
c) The limiting values are stress ratings only. Operating the part at these values is not recommended, and proper operation is not
guaranteed. The conditions for functional operation are specified in Table 16
.
[2] Maximum/minimum voltage above the maximum operating voltage (see Table 16
) and below ground that can be applied for a short time
(< 10 ms) to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.
[3] Including voltage on outputs in 3-state mode.
[4] V
DD
present or not present. Compliant with the I
2
C-bus standard. 5.5 V can be applied to this pin when V
DD
is powered down.
[5] See Table 18
for maximum operating voltage.
[6] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined
based on required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details.
[7] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
Table 12. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
[1]
Symbol Parameter Conditions Min Max Unit
V
DD
supply voltage (core and external rail)
[2]
0.5 +4.6 V
V
I
input voltage 5 V tolerant I/O
pins; only valid
when the V
DD
supply voltage is
present
[2][3]
0.5 +5.5 V
5 V tolerant
open-drain pins
PIO0_4 and
PIO0_5
[2][4]
0.5 +5.5 V
V
IA
analog input voltage pin configured as
analog input
[2][5]
0.5 4.6 V
I
DD
supply current per supply pin - 100 mA
I
SS
ground current per ground pin - 100 mA
I
latch
I/O latch-up current (0.5V
DD
) < V
I
<
(1.5V
DD
);
T
j
< 125 C
- 100 mA
T
stg
storage temperature non-operating
[6]
65 +150 C
T
j(max)
maximum junction temperature - 150 C
P
tot(pack)
total power dissipation (per package) based on package
heat transfer, not
device power
consumption
-1.5W
V
ESD
electrostatic discharge voltage human body
model; all pins
[7]
- +6500 V