Datasheet

LPC1102_1104 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 26 September 2013 25 of 43
NXP Semiconductors
LPC1102/1104
32-bit ARM Cortex-M0 microcontroller
Conditions: V
DD
= 3.3 V; sleep mode entered from flash; all peripherals disabled in the
SYSAHBCLKCTRL register (SYSAHBCLKCTRL= 0x1F); all peripheral clocks disabled; internal
pull-up resistors disabled; BOD disabled; low-current mode.
(1) System PLL disabled; IRC enabled.
(2) System PLL enabled; IRC disabled.
Fig 8. Sleep mode: Typical supply current I
DD
versus temperature for different system
clock frequencies
Conditions: BOD disabled; all oscillators and analog blocks disabled in the PDSLEEPCFG register
(PDSLEEPCFG = 0x0000 18FF).
Remark: Before entering deep-sleep mode, you must write a 0 to bit 4 and bit 5 of the GPIO0DATA
register at location 0x5000 3FFC and a 1 to bit 4 and bit 5 of the GPIO0DIR register at location
0x5000 8000.
Fig 9. Deep-sleep mode: Typical supply current I
DD
versus temperature for different
supply voltages V
DD
temperature (°C)
−40 853510 60−15
002aaf982
2
4
6
I
DD
(mA)
0
12 MHz
(1)
24 MHz
(2)
36 MHz
(2)
48 MHz
(2)
002aaf977
temperature (°C)
−40 853510 60−15
2.5
4.5
3.5
5.5
I
DD
(μA)
1.5
V
DD
= 3.3 V, 3.6 V
1.8 V