Datasheet
HEF4094B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 11 — 29 August 2013 8 of 20
NXP Semiconductors
HEF4094B
8-stage shift-and-store register
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C
L
in pF).
t
PLZ
LOW to OFF-state
propagation delay
OE to QPn;
see Figure 9
5 V - 80 160 ns
10 V - 40 80 ns
15 V - 30 60 ns
t
su
set-up time D to CP;
see Figure 10
5 V 6030- ns
10 V 20 10 - ns
15 V 15 5 - ns
t
h
hold time D to CP;
see Figure 10
5 V +5 15 - ns
10 V 20 5 - ns
15 V 20 5 - ns
t
W
pulse width minimum LOW
clock pulse;
see Figure 7
5 V 6030- ns
10 V 30 15 - ns
15 V 24 12 - ns
minimum HIGH
strobe pulse;
see Figure 8
5 V 4020- ns
10 V 30 15 - ns
15 V 24 12 - ns
f
max
maximum frequency see Figure 7 5 V 5 10 - MHz
10 V 11 22 - MHz
15 V 1428- MHz
Table 7. Dynamic characteristics
…continued
V
SS
= 0 V; T
amb
= 25
C; for test circuit see Figure 11; unless otherwise specified.
Symbol Parameter Conditions V
DD
Extrapolation formula Min Typ Max Unit
Table 8. Dynamic power dissipation
V
SS
= 0 V; t
r
= t
f
20 ns; T
amb
= 25
C.
Symbol Parameter V
DD
Typical formula for P
D
(W) where:
P
D
dynamic power
dissipation
5 V P
D
= 2100 f
i
+ (f
o
C
L
) V
DD
2
f
i
= input frequency in MHz,
f
o
= output frequency in MHz,
C
L
= output load capacitance in pF,
V
DD
= supply voltage in V,
(f
o
C
L
) = sum of the outputs.
10 V P
D
= 9700 f
i
+ (f
o
C
L
) V
DD
2
15 V P
D
= 26000 f
i
+ (f
o
C
L
) V
DD
2