Datasheet

HEF4094B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 11 — 29 August 2013 11 of 20
NXP Semiconductors
HEF4094B
8-stage shift-and-store register
a. Input waveform
b. Test circuit
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
C
L
= load capacitance including jig and probe capacitance.
R
L
= load resistance.
R
T
= termination resistance should be equal to the output impedance Z
o
of the pulse generator.
Fig 11. Test circuit
V
M
V
M
t
W
t
W
10 %
90 %
10 %
90 %
0 V
V
I
V
I
negative
pulse
positive
pulse
0 V
V
M
V
M
90 %
10 %
90 %
10 %
t
f
t
r
t
r
t
f
001aaj781
001aaj915
V
EXT
V
DD
V
I
V
O
DUT
C
L
R
T
R
L
G
Table 10. Test data
Supply voltage Input V
EXT
Load
V
DD
V
I
t
r
, t
f
t
PHL
, t
PLH
t
PHZ
, t
PZH
t
PLZ
, t
PZL
C
L
R
L
5 V to 15 V V
SS
or V
DD
 20 ns open V
SS
V
DD
50 pF 1 k