Datasheet

HEF4053B All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet Rev. 11 — 11 September 2014 3 of 20
NXP Semiconductors
HEF4053B
Triple single-pole double-throw analog switch
6. Pinning information
6.1 Pinning
6.2 Pin description
Fig 4. Schematic diagram (one switch)
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nYn
nZ
V
EE
from decoder
and enable logic
V
DD
V
DD
Fig 5. Pin configuration for SOT38-4 (DIP16) and
SOT109-1 (SO16)
Fig 6. Pin configuration for SOT403-1 (TSSOP16)
HEF4053B
2Y1 V
DD
2Y0 2Z
3Y1 1Z
3Z 1Y1
3Y0 1Y0
ES1
V
EE
S2
V
SS
S3
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1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
HEF4053B
2Y1 V
DD
2Y0 2Z
3Y1 1Z
3Z 1Y1
3Y0 1Y0
ES1
V
EE
S2
V
SS
S3
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1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 2. Pin description
Symbol Pin Description
E
6 enable input (active LOW)
V
EE
7 supply voltage
V
SS
8 ground supply voltage
S1, S2, S3 11, 10, 9 select input
1Y0, 2Y0, 3Y0 12, 2, 5 independent input or output
1Y1, 2Y1, 3Y1 13, 1, 3 independent input or output
1Z, 2Z, 3Z 14, 15, 4 independent output or input
V
DD
16 supply voltage