Datasheet

56F826 Technical Data, Rev. 14
46 Freescale Semiconductor
Figure 3-28 TXD Pulse Width
3.13 JTAG Timing
Figure 3-29 Test Clock Input Timing Diagram
Table 3-17 JTAG Timing
1, 3
Operating Conditions: V
SSIO
=V
SS
= V
SSA
= 0V, V
DDA
=V
DDIO
=3.0–3.6V, V
DD
= 2.25–2.75V, T
A
= –40° to +85°C, C
L
≤ 50pF, f
op
= 80MHz
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz
operation, T = 12.5ns.
Characteristic Symbol Min Max Unit
TCK frequency of operation
2
2. TCK frequency of operation must be less than 1/8 the processor rate.
3. Parameters listed are guaranteed by design.
f
OP
DC 10 MHz
TCK cycle time t
CY
100 — ns
TCK clock pulse width t
PW
50 — ns
TMS, TDI data set-up time t
DS
0.4 — ns
TMS, TDI data hold time t
DH
1.2 — ns
TCK low to TDO data valid t
DV
— 26.6 ns
TCK low to TDO tri-state t
TS
— 23.5 ns
TRST
assertion time t
TRST
50 — ns
DE
assertion time t
DE
4T — ns
TXD
SCI receive
data pin
(Input)
TXD
PW
TCK
(Input)
V
M
V
IL
V
M
= V
IL
+ (V
IH
– V
IL
)/2
V
M
V
IH
t
PW
t
CY
t
PW