Datasheet

Synchronous Serial Interface (SSI) Timing
56F826 Technical Data, Rev. 14
Freescale Semiconductor 43
Synchronous Operation (in addition to standard external clock parameters)
SRXD Setup time before STCK low - Slave t
TSS
4——
SRXD Hold time after STCK low - Slave t
THS
4——
1. Slave mode is externally generated clocks and frame syncs
2. Max clock frequency is IP_clk/4 = 40MHz / 4 = 10MHz for an 80MHz part.
3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)
and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync
have been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS
in the tables and in the figures.
4. 50% duty cycle
5. bl = bit length; wl = word length
Table 3-14 SSI Slave Mode
1
Switching Characteristics
Operating Conditions: V
SSIO
= V
SS
= V
SSA
= 0V, V
DDA
= V
DDIO
= 3.0–3.6V, V
DD
= 2.25–2.75V, T
A
= –40 ° to +85 ° C, C
L
≤ 50pF, f
op
= 80MHz
Parameter Symbol Min Typ Max Units