Datasheet

Synchronous Serial Interface (SSI) Timing
56F826 Technical Data, Rev. 14
Freescale Semiconductor 41
Figure 3-24 Master Mode Timing Diagram
3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)
and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have
been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS in the
tables and in the figures.
4. 50% duty cycle
5. bl = bit length; wl = word length
t
THM
t
TSM
t
HM
t
SM
t
RFSWLM
t
RFSWHM
t
RFBLM
t
RFSBHM
t
TXHIM
t
TXNVM
t
TXVM
t
TXEM
t
TFSWLM
t
TFSWHM
t
TFSBLM
t
TFSBHM
t
SCKL
t
SCKW
t
SCKH
First Bit Last Bit
STCK output
STFS (bl) output
STFS (wl) output
STXD
SRCK output
SRFS (bl) output
SRFS (wl) output
SRXD