Datasheet

56F826 Technical Data, Rev. 14
40 Freescale Semiconductor
3.10 Synchronous Serial Interface (SSI) Timing
Table 3-13 SSI Master Mode
1
Switching Characteristics
Operating Conditions: V
SSIO
= V
SS
= V
SSA
= 0V, V
DDA
= V
DDIO
= 3.0–3.6V, V
DD
= 2.25–2.75V, T
A
= –40° to +85°C, C
L
≤ 50pF, f
op
= 80MHz
1. Master mode is internally generated clocks and frame syncs
Parameter Symbol Min Typ Max Units
STCK frequency fs
10
2
2. Max clock frequency is IP_clk/4 = 40MHz / 4 = 10MHz for an 80MHz part.
MHz
STCK period
3
t
SCKW
100 — — ns
STCK high time t
SCKH
50
4
——ns
STCK low time t
SCKL
50
4
——ns
Output clock rise/fall time (STCK, SRCK) —
4
—ns
Delay from STCK high to STFS (bl) high - Master
5
t
TFSBHM
0.1 — 0.5 ns
Delay from STCK high to STFS (wl) high - Master
5
t
TFSWHM
0.1 — 0.5 ns
Delay from SRCK high to SRFS (bl) high - Master
5
t
RFSBHM
0.6 — 1.3 ns
Delay from SRCK high to SRFS (wl) high - Master
5
t
RFSWHM
0.6 — 1.3 ns
Delay from STCK high to STFS (bl) low - Master
5
t
TFSBLM
-1.0 — -0.1 ns
Delay from STCK high to STFS (wl) low - Master
5
t
TFSWLM
-1.0 — -0.1 ns
Delay from SRCK high to SRFS (bl) low - Master
5
t
RFSBLM
-0.1 — 0 ns
Delay from SRCK high to SRFS (wl) low - Master
5
t
RFSWLM
-0.1 — 0 ns
STCK high to STXD enable from high impedance - Master t
TXEM
20 — 22 ns
STCK high to STXD valid - Master t
TXVM
24 — 26 ns
STCK high to STXD not valid - Master t
TXNVM
0.1 — 0.2 ns
STCK high to STXD high impedance - Master t
TXHIM
24 — 25.5 ns
SRXD Setup time before SRCK low - Master t
SM
4—— ns
SRXD Hold time after SRCK low - Master t
HM
4—— ns
Synchronous Operation (in addition to standard internal clock parameters)
SRXD Setup time before STCK low - Master t
TSM
4——
SRXD Hold time after STCK low - Master t
THM
4——