Datasheet

Serial Peripheral Interface (SPI) Timing
56F826 Technical Data, Rev. 14
Freescale Semiconductor 37
3.9 Serial Peripheral Interface (SPI) Timing
Table 3-12 SPI Timing
1
Operating Conditions: V
SSIO
=V
SS
= V
SSA
= 0V, V
DDA
=V
DDIO
=3.0–3.6V, V
DD
= 2.25–2.75V, T
A
= –40° to +85°C, C
L
≤ 50pF, f
op
= 80MHz
1. Parameters are guaranteed by design.
Characteristic Symbol Min Max Unit See Figure
Cycle time
Master
Slave
t
C
50
25
—
—
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
Enable lead time
Master
Slave
t
ELD
—
25
—
—
ns
ns
Figure 3-23
Enable lag time
Master
Slave
t
ELG
—
100
—
—
ns
ns
Figure 3-23
Clock (SCLK) high time
Master
Slave
t
CH
24
12
—
—
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
Clock (SCLK) low time
Master
Slave
t
CL
24.1
12
—
—
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
Data set-up time required for inputs
Master
Slave
t
DS
20
0
—
—
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
Data hold time required for inputs
Master
Slave
t
DH
0
2
—
—
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
Access time (time to data active from high-impedance state)
Slave
t
A
4.8 15 ns
Figure 3-23
Disable time (hold time to high-impedance state)
Slave
t
D
3.7 15.2 ns
Figure 3-23
Data Valid for outputs
Master
Slave (after enable edge)
t
DV
—
—
4.5
20.4
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
Data invalid
Master
Slave
t
DI
0
0
—
—
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
Rise time
Master
Slave
t
R
—
—
11.5
10.0
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
Fall time
Master
Slave
t
F
—
—
9.7
9.0
ns
ns
Figures
3-20, 3-21,
3-22, 3-23