Datasheet

External Bus Asynchronous Timing
56F826 Technical Data, Rev. 14
Freescale Semiconductor 33
Figure 3-13 External Bus Asynchronous Timing
A0–A15,
PS
, DS
(See Note)
WR
D0–D15
RD
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Data InData Out
t
AWR
t
ARDA
t
ARDD
t
RDA
t
RD
t
RDRD
t
RDWR
t
WRWR
t
WR
t
DOS
t
WRD
t
WRRD
t
AD
t
DOH
t
DRD
t
RDD