Datasheet

56F826 Technical Data, Rev. 14
32 Freescale Semiconductor
Input Data Hold to RD
Deasserted t
DRD
0—ns
RD
Assertion Width
Wait states = 0
Wait states > 0
t
RD
19
(T*WS) + 19
—
—
ns
ns
Address Valid to Input Data Valid
Wait states = 0
Wait states > 0
t
AD
—
—
1
(T*WS) + 1
ns
ns
Address Valid to RD
Asserted t
ARDA
-4.4 — ns
RD
Asserted to Input Data Valid
Wait states = 0
Wait states > 0
t
RDD
—
—
2.4
(T*WS) + 2.4
ns
ns
WR
Deasserted to RD Asserted t
WRRD
6.8 — ns
RD
Deasserted to RD Asserted t
RDRD
0—ns
WR
Deasserted to WR Asserted t
WRWR
14.1 — ns
RD
Deasserted to WR Asserted t
RDWR
12.8 — ns
1. Timing is both wait state- and frequency-dependent. In the formulas listed, WS = the number of wait states and
T = Clock Period. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
To calculate the required access time for an external memory for any frequency < 80Mhz, use this formula:
Top = Clock period @ desired operating frequency
WS = Number of wait states
Memory Access Time = (Top*WS) + (Top- 11.5)
Table 3-10 External Bus Asynchronous Timing
1, 2
(Continued)
Operating Conditions: V
SSIO
= V
SS
= V
SSA
= 0V, V
DDA
= V
DDIO
= 3.0–3.6V, V
DD
= 2.25–2.75V, T
A
= –40° to +85°C, C
L
≤ 50pF, f
op
= 80MHz
Characteristic Symbol
Min
Max
Unit