Datasheet

56F826 Technical Data, Rev. 14
24 Freescale Semiconductor
V
DD
should not be allowed to rise early (1). This is usually avoided by running the regulator for the V
DD
supply (2.5V) from the voltage generated by the 3.3V V
DDIO
supply, see Figure 3-3. This keeps V
DD
from
rising faster than V
DDIO
.
V
DD
should not rise so late that a large voltage difference is allowed between the two supplies (2).
Typically this situation is avoided by using external discrete diodes in series between supplies, as shown
in Figure 3-3. The series diodes forward bias when the difference between V
DDIO
and V
DD
reaches
approximately 1.4, causing V
DD
to rise as V
DDIO
ramps up. When the V
DD
regulator begins proper
operation, the difference between supplies will typically be 0.8V and conduction through the diode chain
reduces to essentially leakage current. During supply sequencing, the following general relationship
should be adhered to:
V
DDIO
> V
DD
> (V
DDIO
- 1.4V)
In practice, V
DDA
is typically connected directly to V
DDIO
with some filtering.
Figure 3-3 Example Circuit to Control Supply Sequencing
3.4 AC Electrical Characteristics
Timing waveforms in Section 3.4 are tested using the V
IL
and V
IH
levels specified in the DC Characteristics
table. The levels of V
IH
and V
IL
for an input signal are shown in Figure 3-4.
Figure 3-4 Input Signal Measurement References
Figure 3-5 shows the definitions of the following signal states:
• Active state, when a bus or signal is driven, and enters a low impedance state
• Tri-stated, when a bus or signal is placed in a high impedance state
• Data Valid state, when a signal level has reached V
OL
or V
OH
• Data Invalid state, when a signal level is in transition between V
OL
and V
OH
3.3V
Regulator
2.5V
Regulator
Supply
V
DD
V
DDIO,
V
DDA
V
IH
V
IL
Fall Time
Input Signal
Note: The midpoint is V
IL
+ (V
IH
– V
IL
)/2.
Midpoint1
Low High
Pulse Width
90%
50%
10%
Rise Time