Datasheet

Signals and Package Information
56F826 Technical Data, Rev. 14
Freescale Semiconductor 17
IRQA
32 Input
(Schmitt)
External Interrupt Request A—The IRQA input is a synchronized external
interrupt request that indicates that an external device is requesting service. It
can be programmed to be level-sensitive or negative-edge-triggered. If
level-sensitive triggering is selected, an external pull-up resistor is required for
wired-OR operation.
If the processor is in the Stop state and IRQA
is asserted, the processor will exit
the Stop state.
IRQB
33 Input
(Schmitt)
External Interrupt Request B—The IRQB input is an external interrupt request
that indicates that an external device is requesting service. It can be
programmed to be level-sensitive or negative-edge-triggered. If level-sensitive
triggering is selected, an external pull-up resistor is required for wired-OR
operation.
RESET 45 Input
(Schmitt)
Reset—This input is a direct hardware reset on the processor. When RESET is
asserted low, the device is initialized and placed in the Reset state. A Schmitt
trigger input is used for noise immunity. When the RESET pin is deasserted, the
initial chip operating mode is latched from the external boot pin. The internal
reset signal will be deasserted synchronous with the internal clocks, after a fixed
number of internal clocks.
To ensure complete hardware reset, RESET
and TRST should be asserted
together. The only exception occurs in a debugging environment when a
hardware device reset is required and it is necessary not to reset the
OnCE/JTAG module. In this case, assert RESET
, but do not assert TRST.
EXTBOOT 25 Input
(Schmitt)
External Boot—This input is tied to V
DD
to force device to boot from off-chip
memory. Otherwise, it is tied to ground.
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name
Pin No. Type Description