Datasheet

56F826 Technical Data, Rev. 14
12 Freescale Semiconductor
A8
(GPIOA0)
14 Output
Input/Output
Address Bus—A8–A15 specify the address for external program or data
memory accesses.
Port A GPIO—These eight General Purpose I/O (GPIO) pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
A9
(GPIOA1)
13
A10
(GPIOA2)
12
A11
(GPIOA3)
11
A12
(GPIOA4)
10
A13
(GPIOA5)
9
A14
(GPIOA6)
8
A15
(GPIOA7)
7
D0 34 Input/Output Data Bus— D0–D15 specify the data for external program or data memory
accesses. D0–D15 are tri-stated when the external bus is inactive.
D1 35
D2 36
D3 37
D4 38
D5 39
D6 40
D7 41
D8 42
D9 43
D10 44
D11 46
D12 47
D13 48
D14 49
D15 50
PS
29 Output Program Memory Select—PS is asserted low for external program memory
access.
DS
28 Output Data Memory Select—DS is asserted low for external data memory access.
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name
Pin No. Type Description