Datasheet

Signals and Package Information
56F826 Technical Data, Rev. 14
Freescale Semiconductor 11
XTAL
(CLOCKIN)
62 Output
Input
Crystal Oscillator Output—This output connects the internal crystal oscillator
output to an external crystal or ceramic resonator. If an external clock source
over 4MHz is used, XTAL must be used as the input and EXTAL connected to
V
SS
. For more information, please refer to Section 3.6.3.
External Clock Input—This input should be asserted when using an external
clock or ceramic resonator.
CLKO 65 Output Clock Output—This pin outputs a buffered clock signal. By programming the
CLKO Select Register (CLKOSR), the user can select between outputting a
version of the signal applied to XTAL and a version of the device master clock at
the output of the PLL. The clock frequency on this pin can be disabled by
programming the CLKO Select Register (CLKOSR).
A0
(GPIOE0)
24 Output
Input/Output
Address Bus—A0–A7 specify the address for external program or data memory
accesses.
Port E GPIO—These eight General Purpose I/O (GPIO) pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
A1
(GPIOE1)
23
A2
(GPIOE2)
22
A3
(GPIOE3)
21
A4
(GPIOE4)
18
A5
(GPIOE5)
17
A6
(GPIOE6)
16
A7
(GPIOE7)
15
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name
Pin No. Type Description