Datasheet

56F805 Technical Data, Rev. 16
8 Freescale Semiconductor
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F805 are organized into functional groups, as shown in Table 2-1
and as illustrated in Figure 2-1. In Table 2-2 through Table 2-18, each table row describes the signal or
signals present on a pin.
Table 2-1 Functional Group Pin Allocations
Functional Group
Number of
Pins
Detailed
Description
Power (V
DD
or V
DDA
)9Table 2-2
Ground (V
SS
or V
SSA
)9Table 2-3
Supply Capacitors and V
PP
3 Table 2-4
PLL and Clock 3 Table 2-5
Address Bus
1
16 Table 2-6
Data Bus 16 Table 2-7
Bus Control 4 Table 2-8
Interrupt and Program Control 5 Table 2-9
Dedicated General Purpose Input/Output 14 Table 2-10
Pulse Width Modulator (PWM) Port 26 Table 2-11
Serial Peripheral Interface (SPI) Port
1
1. Alternately, GPIO pins
4 Table 2-12
Quadrature Decoder Port
2
2. Alternately, Quad Timer pins
8 Table 2-13
Serial Communications Interface (SCI) Port
1
4 Table 2-14
CAN Port 2 Table 2-15
Analog to Digital Converter (ADC) Port 9 Table 2-16
Quad Timer Module Ports 6 Table 2-17
JTAG/On-Chip Emulation (OnCE) 6 Table 2-18