Datasheet
Table Of Contents
- Part 1 Overview
- Part 2 Signal/Connection Descriptions
- 2.1 Introduction
- 2.2 Power and Ground Signals
- 2.3 Clock and Phase Locked Loop Signals
- 2.4 Address, Data, and Bus Control Signals
- 2.5 Interrupt and Program Control Signals
- 2.6 GPIO Signals
- 2.7 Pulse Width Modulator (PWM) Signals
- 2.8 Serial Peripheral Interface (SPI) Signals
- 2.9 Quadrature Decoder Signals
- 2.10 Serial Communications Interface (SCI) Signals
- 2.11 CAN Signals
- 2.12 Analog-to-Digital Converter (ADC) Signals
- 2.13 Quad Timer Module Signals
- 2.14 JTAG/OnCE
- Part 3 Specifications
- 3.1 General Characteristics
- 3.2 DC Electrical Characteristics
- 3.3 AC Electrical Characteristics
- 3.4 Flash Memory Characteristics
- 3.5 External Clock Operation
- 3.6 External Bus Asynchronous Timing
- 3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
- 3.8 Serial Peripheral Interface (SPI) Timing
- 3.9 Quad Timer Timing
- 3.10 Quadrature Decoder Timing
- 3.11 Serial Communication Interface (SCI) Timing
- 3.12 Analog-to-Digital Converter (ADC) Characteristics
- 3.13 Controller Area Network (CAN) Timing
- 3.14 JTAG Timing
- Part 4 Packaging
- Part 5 Design Considerations
- Part 6 Ordering Information
Product Documentation
56F805 Technical Data, Rev. 16
Freescale Semiconductor 7
1.4 Product Documentation
The four documents listed in Table 2-1 are required for a complete description and proper design with the
56F805. Documentation is available from local Freescale distributors, Freescale semiconductor sales
offices, Freescale Literature Distribution Centers, or online at www.freescale.com.
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
Table 1-1 Chip Documentation
Topic Description Order Number
56800E
Family Manual
Detailed description of the 56800 family architecture, and
16-bit core processor and the instruction set
56800EFM
DSP56F801/803/805/807
User’s Manual
Detailed description of memory, peripherals, and interfaces
of the 56F801, 56F803, 56F805, and 56F807
DSP56F801-7UM
56F805
Technical Data Sheet
Electrical and timing specifications, pin descriptions, and
package descriptions (this document)
DSP56F805
56F805
Errata
Details any chip issues that might be present DSP56F805E
OVERBAR
This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted” A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.
Examples: Signal/Symbol Logic State Signal State
Voltage
1
1. Values for V
IL
, V
OL
, V
IH
, and V
OH
are defined by individual product specifications.
PIN True Asserted V
IL
/V
OL
PIN False Deasserted V
IH
/V
OH
PIN True Asserted V
IH
/V
OH
PIN False Deasserted V
IL
/V
OL