Datasheet
Table Of Contents
- Part 1 Overview
- Part 2 Signal/Connection Descriptions
- 2.1 Introduction
- 2.2 Power and Ground Signals
- 2.3 Clock and Phase Locked Loop Signals
- 2.4 Address, Data, and Bus Control Signals
- 2.5 Interrupt and Program Control Signals
- 2.6 GPIO Signals
- 2.7 Pulse Width Modulator (PWM) Signals
- 2.8 Serial Peripheral Interface (SPI) Signals
- 2.9 Quadrature Decoder Signals
- 2.10 Serial Communications Interface (SCI) Signals
- 2.11 CAN Signals
- 2.12 Analog-to-Digital Converter (ADC) Signals
- 2.13 Quad Timer Module Signals
- 2.14 JTAG/OnCE
- Part 3 Specifications
- 3.1 General Characteristics
- 3.2 DC Electrical Characteristics
- 3.3 AC Electrical Characteristics
- 3.4 Flash Memory Characteristics
- 3.5 External Clock Operation
- 3.6 External Bus Asynchronous Timing
- 3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
- 3.8 Serial Peripheral Interface (SPI) Timing
- 3.9 Quad Timer Timing
- 3.10 Quadrature Decoder Timing
- 3.11 Serial Communication Interface (SCI) Timing
- 3.12 Analog-to-Digital Converter (ADC) Characteristics
- 3.13 Controller Area Network (CAN) Timing
- 3.14 JTAG Timing
- Part 4 Packaging
- Part 5 Design Considerations
- Part 6 Ordering Information
56F805 Technical Data, Rev. 16
42 Freescale Semiconductor
Figure 3-26 TXD Pulse Width
3.12 Analog-to-Digital Converter (ADC) Characteristics
Table 3-16 ADC Characteristics
Characteristic Symbol Min Typ Max Unit
ADC input voltages V
ADCIN
0
1
—
V
REF
2
V
Resolution R
ES
12 — 12 Bits
Integral Non-Linearity
3
INL — +/-2.5 +/-4
LSB
4
Differential Non-Linearity DNL — +/- 0.9 +/-1
LSB
4
Monotonicity GUARANTEED
ADC internal clock
5
f
ADIC
0.5 — 5 MHz
Conversion range R
AD
V
SSA
—V
DDA
V
Conversion time t
ADC
—6 —
t
AIC
cycles
6
Sample time t
ADS
—1 —
t
AIC
cycles
6
Input capacitance C
ADI
—5 —
pF
6
Gain Error (transfer gain)
5
E
GAIN
.95 1.00 1.10 —
Offset Voltage
5
V
OFFSET
-80 -15 +20 mV
Total Harmonic Distortion
5
THD 60 64 — dB
Signal-to-Noise plus Distortion
5
SINAD 55 60 — dB
Effective Number Of Bits
5
ENOB 9 10 — bit
Spurious Free Dynamic Range
5
SFDR 65 70 — dB
Bandwidth BW — 100 — KHz
TXD
SCI receive
data pin
(Input)
TXD
PW