Datasheet

56F805 Technical Data, Rev. 16
40 Freescale Semiconductor
3.9 Quad Timer Timing
Figure 3-23 Timer Timing
3.10 Quadrature Decoder Timing
Table 3-13 Timer Timing
1, 2
Operating Conditions: V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6V, T
A
= –40° to +85°C, C
L
≤ 50pF, f
OP
= 80MHz
1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
Characteristic Symbol Min Max Unit
Timer input period P
IN
4T+6 — ns
Timer input high/low period P
INHL
2T+3 — ns
Timer output period P
OUT
2T — ns
Timer output high/low period P
OUTHL
1T — ns
Table 3-14 Quadrature Decoder Timing
1, 2
Operating Conditions: V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6V, T
A
= –40° to +85°C, C
L
< 50pF, f
OP
= 80MHz
1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns. V
SS
= 0V, V
DD
= 3.0–3.6V,
T
A
= –40° to +85°C, C
L
≤ 50pF.
2. Parameters listed are guaranteed by design.
Characteristic Symbol Min Max Unit
Quadrature input period P
IN
8T+12 — ns
Quadrature input high/low period P
HL
4T+6 — ns
Quadrature phase period P
PH
2T+3 — ns
Timer Inputs
Timer Outputs
P
INHL
P
INHL
P
IN
P
OUTHL
P
OUTHL
P
OUT