Datasheet
Table Of Contents
- Part 1 Overview
- Part 2 Signal/Connection Descriptions
- 2.1 Introduction
- 2.2 Power and Ground Signals
- 2.3 Clock and Phase Locked Loop Signals
- 2.4 Address, Data, and Bus Control Signals
- 2.5 Interrupt and Program Control Signals
- 2.6 GPIO Signals
- 2.7 Pulse Width Modulator (PWM) Signals
- 2.8 Serial Peripheral Interface (SPI) Signals
- 2.9 Quadrature Decoder Signals
- 2.10 Serial Communications Interface (SCI) Signals
- 2.11 CAN Signals
- 2.12 Analog-to-Digital Converter (ADC) Signals
- 2.13 Quad Timer Module Signals
- 2.14 JTAG/OnCE
- Part 3 Specifications
- 3.1 General Characteristics
- 3.2 DC Electrical Characteristics
- 3.3 AC Electrical Characteristics
- 3.4 Flash Memory Characteristics
- 3.5 External Clock Operation
- 3.6 External Bus Asynchronous Timing
- 3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
- 3.8 Serial Peripheral Interface (SPI) Timing
- 3.9 Quad Timer Timing
- 3.10 Quadrature Decoder Timing
- 3.11 Serial Communication Interface (SCI) Timing
- 3.12 Analog-to-Digital Converter (ADC) Characteristics
- 3.13 Controller Area Network (CAN) Timing
- 3.14 JTAG Timing
- Part 4 Packaging
- Part 5 Design Considerations
- Part 6 Ordering Information

Serial Peripheral Interface (SPI) Timing
56F805 Technical Data, Rev. 16
Freescale Semiconductor 37
3.8 Serial Peripheral Interface (SPI) Timing
Table 3-12 SPI Timing
1
Operating Conditions: V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40° to +85°C, C
L
≤ 50pF, f
OP
= 80MHz
1. Parameters listed are guaranteed by design.
Characteristic Symbol Min Max Unit See Figure
Cycle time
Master
Slave
t
C
50
25
—
—
ns
ns
Figures
3-19, 3-20,
3-21, 3-22
Enable lead time
Master
Slave
t
ELD
—
25
—
—
ns
ns
Figure 3-22
Enable lag time
Master
Slave
t
ELG
—
100
—
—
ns
ns
Figure 3-22
Clock (SCLK) high time
Master
Slave
t
CH
17.6
12.5
—
—
ns
ns
Figures
3-19, 3-20,
3-21, 3-22
Clock (SCLK) low time
Master
Slave
t
CL
24.1
25
—
—
ns
ns
Figure 3-22
Data set-up time required for inputs
Master
Slave
t
DS
20
0
—
—
ns
ns
Figures
3-19, 3-20,
3-21, 3-22
Data hold time required for inputs
Master
Slave
t
DH
0
2
—
—
ns
ns
Figures
3-19, 3-20,
3-21, 3-22
Access time (time to data active from
high-impedance state)
Slave
t
A
4.8 15 ns
Figure 3-22
Disable time (hold time to high-impedance state)
Slave
t
D
3.7 15.2 ns
Figure 3-22
Data Valid for outputs
Master
Slave (after enable edge)
t
DV
—
—
4.5
20.4
ns
ns
Figures
3-19, 3-20,
3-21, 3-22
Data invalid
Master
Slave
t
DI
0
0
—
—
ns
ns
Figures
3-19, 3-20,
3-21, 3-22
Rise time
Master
Slave
t
R
—
—
11.5
10.0
ns
ns
Figures
3-19, 3-20,
3-21, 3-22
Fall time
Master
Slave
t
F
—
—
9.7
9.0
ns
ns
Figures
3-19, 3-20,
3-21, 3-22