Datasheet
Table Of Contents
- Part 1 Overview
- Part 2 Signal/Connection Descriptions
- 2.1 Introduction
- 2.2 Power and Ground Signals
- 2.3 Clock and Phase Locked Loop Signals
- 2.4 Address, Data, and Bus Control Signals
- 2.5 Interrupt and Program Control Signals
- 2.6 GPIO Signals
- 2.7 Pulse Width Modulator (PWM) Signals
- 2.8 Serial Peripheral Interface (SPI) Signals
- 2.9 Quadrature Decoder Signals
- 2.10 Serial Communications Interface (SCI) Signals
- 2.11 CAN Signals
- 2.12 Analog-to-Digital Converter (ADC) Signals
- 2.13 Quad Timer Module Signals
- 2.14 JTAG/OnCE
- Part 3 Specifications
- 3.1 General Characteristics
- 3.2 DC Electrical Characteristics
- 3.3 AC Electrical Characteristics
- 3.4 Flash Memory Characteristics
- 3.5 External Clock Operation
- 3.6 External Bus Asynchronous Timing
- 3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
- 3.8 Serial Peripheral Interface (SPI) Timing
- 3.9 Quad Timer Timing
- 3.10 Quadrature Decoder Timing
- 3.11 Serial Communication Interface (SCI) Timing
- 3.12 Analog-to-Digital Converter (ADC) Characteristics
- 3.13 Controller Area Network (CAN) Timing
- 3.14 JTAG Timing
- Part 4 Packaging
- Part 5 Design Considerations
- Part 6 Ordering Information
Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F805 Technical Data, Rev. 16
Freescale Semiconductor 35
Figure 3-12 Asynchronous Reset Timing
Figure 3-13 External Interrupt Timing (Negative-Edge-Sensitive)
Figure 3-14 External Level-Sensitive Interrupt Timing
First Fetch
A0–A15,
D0–D15
PS
, DS,
RD
, WR
RESET
First Fetch
t
RDA
t
RA
t
RAZ
IRQA
IRQB
t
IRW
A0–A15,
PS
, DS,
RD, WR
IRQA,
IRQB
First Interrupt Instruction Execution
a) First Interrupt Instruction Execution
Purpose
I/O Pin
IRQA
,
IRQB
b) General Purpose I/O
t
IG
t
IDM