Datasheet
Table Of Contents
- Part 1 Overview
- Part 2 Signal/Connection Descriptions
- 2.1 Introduction
- 2.2 Power and Ground Signals
- 2.3 Clock and Phase Locked Loop Signals
- 2.4 Address, Data, and Bus Control Signals
- 2.5 Interrupt and Program Control Signals
- 2.6 GPIO Signals
- 2.7 Pulse Width Modulator (PWM) Signals
- 2.8 Serial Peripheral Interface (SPI) Signals
- 2.9 Quadrature Decoder Signals
- 2.10 Serial Communications Interface (SCI) Signals
- 2.11 CAN Signals
- 2.12 Analog-to-Digital Converter (ADC) Signals
- 2.13 Quad Timer Module Signals
- 2.14 JTAG/OnCE
- Part 3 Specifications
- 3.1 General Characteristics
- 3.2 DC Electrical Characteristics
- 3.3 AC Electrical Characteristics
- 3.4 Flash Memory Characteristics
- 3.5 External Clock Operation
- 3.6 External Bus Asynchronous Timing
- 3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
- 3.8 Serial Peripheral Interface (SPI) Timing
- 3.9 Quad Timer Timing
- 3.10 Quadrature Decoder Timing
- 3.11 Serial Communication Interface (SCI) Timing
- 3.12 Analog-to-Digital Converter (ADC) Characteristics
- 3.13 Controller Area Network (CAN) Timing
- 3.14 JTAG Timing
- Part 4 Packaging
- Part 5 Design Considerations
- Part 6 Ordering Information
56F805 Technical Data, Rev. 16
34 Freescale Semiconductor
3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1, 6
Operating Conditions: V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40° to +85°C, C
L
≤ 50pF
1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
Characteristic Symbol Min Max Unit See Figure
RESET
Assertion to Address, Data and Control
Signals High Impedance
t
RAZ
—21nsFigure 3-12
Minimum RESET
Assertion Duration
2
OMR Bit 6 = 0
OMR Bit 6 = 1
2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
• After power-on reset
• When recovering from Stop state
t
RA
275,000T
128T
—
—
ns
ns
Figure 3-12
RESET
Deassertion to First External Address Output t
RDA
33T 34T ns Figure 3-12
Edge-sensitive Interrupt Request Width t
IRW
1.5T — ns Figure 3-13
IRQA
, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction
execution in the interrupt service routine
t
IDM
15T — ns Figure 3-14
IRQA
, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
t
IG
16T — ns Figure 3-14
IRQA
Low to First Valid Interrupt Vector Address Out
recovery from Wait State
3
3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is
not the minimum required so that the IRQA interrupt is accepted.
t
IRI
13T — ns Figure 3-15
IRQA
Width Assertion to Recover from Stop State
4
4. The interrupt instruction fetch is visible on the pins only in Mode 3.
t
IW
2T — ns Figure 3-16
Delay from IRQA
Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
t
IF
—
—
275,000T
12T
ns
ns
Figure 3-16
Duration for Level Sensitive IRQA
Assertion to Cause
the Fetch of First IRQA
Interrupt Instruction (exiting
Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
t
IRQ
—
—
275,000T
12T
ns
ns
Figure 3-17
Delay from Level Sensitive IRQA
Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
t
II
—
—
275,000T
12T
ns
ns
Figure 3-17
RSTO
pulse width
5
normal operation
internal reset mode
5. ET = External Clock period, For an external crystal frequency of 8MHz, ET=125ns.
6. Parameters listed are guaranteed by design.
t
RSTO
63ET
2,097,151ET
ns
ns
Figure 3-18