Datasheet
Table Of Contents
- Part 1 Overview
- Part 2 Signal/Connection Descriptions
- 2.1 Introduction
- 2.2 Power and Ground Signals
- 2.3 Clock and Phase Locked Loop Signals
- 2.4 Address, Data, and Bus Control Signals
- 2.5 Interrupt and Program Control Signals
- 2.6 GPIO Signals
- 2.7 Pulse Width Modulator (PWM) Signals
- 2.8 Serial Peripheral Interface (SPI) Signals
- 2.9 Quadrature Decoder Signals
- 2.10 Serial Communications Interface (SCI) Signals
- 2.11 CAN Signals
- 2.12 Analog-to-Digital Converter (ADC) Signals
- 2.13 Quad Timer Module Signals
- 2.14 JTAG/OnCE
- Part 3 Specifications
- 3.1 General Characteristics
- 3.2 DC Electrical Characteristics
- 3.3 AC Electrical Characteristics
- 3.4 Flash Memory Characteristics
- 3.5 External Clock Operation
- 3.6 External Bus Asynchronous Timing
- 3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
- 3.8 Serial Peripheral Interface (SPI) Timing
- 3.9 Quad Timer Timing
- 3.10 Quadrature Decoder Timing
- 3.11 Serial Communication Interface (SCI) Timing
- 3.12 Analog-to-Digital Converter (ADC) Characteristics
- 3.13 Controller Area Network (CAN) Timing
- 3.14 JTAG Timing
- Part 4 Packaging
- Part 5 Design Considerations
- Part 6 Ordering Information
56F805 Technical Data, Rev. 16
Freescale Semiconductor 3
56F805 Block Diagram
JTAG/
OnCE
Port
Digital Reg
Analog Reg
Low Voltage
Supervisor
Program Controller
and
Hardware Looping Unit
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Address
Generation
Unit
Bit
Manipulation
Unit
PLL
Clock Gen
16-Bit
56800
Core
PAB
PDB
XDB2
CGDB
XAB1
XAB2
XTAL
EXTAL
INTERRUPT
CONTROLS
IPBB
CONTROLS
IPBus Bridge
(IPBB)
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
COP RESET
RESET
IRQA
IRQB
Applica-
tion-Specific
Memory &
Peripherals
Interrupt
Controller
Program Memory
32252 x 16 Flash
512 x 16 SRAM
Boot Flash
2048 x 16 Flash
Data Memory
4096 x 16 Flash
2048 x 16 SRAM
COP/
Watchdog
SPI
or
GPIO
SCI0
or
GPIO
Quad Timer D
/ Alt Func
Quad Timer C
A/D1
A/D2
ADC
4
2
4
4
4
4
6
PWM Outputs
Fault Inputs
PWMA
16 16
VCAPC V
DD
V
SS
V
DDA
V
SSA
6
28 8*
•
•
•
•
•
•
•
•
EXTBOOT
Current Sense Inputs
3
Quadrature
Decoder 0/
Quad Timer A
CAN 2.0A/B
2
CLKO
External
Address Bus
Switch
Bus
Control
External
Data Bus
Switch
External
Bus
Interface
Unit
RD Enable
WR
Enable
DS
Select
PS
Select
10
16
6
A[00:05]
D[00:15]
A[06:15] or
GPIO-E2:E3 &
GPIO-A0:A7
4
4
6
PWM Outputs
Fault Inputs
PWMB
Current Sense Inputs
3
Quadrature
Decoder 1/
Quad B Timer
4
2
SCI1
or
GPIO
2
Dedicated
GPIO
14
VPP
RSTO
VREF
• Up to 40 MIPS at 80MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Hardware DO and REP loops
• MCU-friendly instruction set supports both DSP
and controller functions: MAC, bit manipulation
unit, 14 addressing modes
• 31.5K × 16-bit words (64KB) Program Flash
• 512 × 16-bit words (1KB) Program RAM
•4K × 16-bit words (8KB) Data Flash
•2K × 16-bit words (4KB) Data RAM
•2K × 16-bit words (4KB) Boot Flash
• Up to 64K × 16-bit words (128KB) each of external
Program and Data memory
• Two 6-channel PWM Modules
• Two 4-channel, 12-bit ADCs
• Two Quadrature Decoders
• CAN 2.0 B Module
• Two Serial Communication Interfaces (SCIs)
• Serial Peripheral Interface (SPI)
• Up to four General Purpose Quad Timers
• JTAG/OnCE
TM
port for debugging
• 14 Dedicated and 18 Shared GPIO lines
• 144-pin LQFP Package
*includes TCS pin which is reserved for factory use and is tied to VSS
56F805 General Description