Datasheet

56F805 Technical Data, Rev. 16
26 Freescale Semiconductor
Table 3-7 Flash Timing Parameters
Operating Conditions: V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6V, T
A
= –40° to +85°C, C
L
≤ 50pF
Characteristic Symbol Min Typ Max Unit Figure
Program time
Tprog*
20 – – us Figure 3-4
Erase time
Terase*
20 – – ms Figure 3-5
Mass erase time
Tme*
100 – – ms Figure 3-6
Endurance
1
1. One cycle is equal to an erase program and read.
E
CYC
10,000 20,000 – cycles
Data Retention
1
D
RET
10 30 – years
The following parameters should only be used in the Manual Word Programming Mode
PROG/ERASE to NVSTR set up
time
Tnvs*
–5–usFigure 3-4,
Figure 3-5,
Figure 3-6
NVSTR hold time
Tnvh*
–5–usFigure 3-4,
Figure 3-5
NVSTR hold time (mass erase)
Tnvh1*
– 100 – us Figure 3-6
NVSTR to program set up time
Tpgs*
–10–usFigure 3-4
Recovery time
Trcv*
–1–usFigure 3-4,
Figure 3-5,
Figure 3-6
Cumulative program
HV period
2
2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be pro-
grammed twice before next erase.
Thv
–3–ms Figure 3-4
Program hold time
3
3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.
*The Flash interface unit provides registers for the control of these parameters.
Tpgh
––– Figure 3-4
Address/data set up time
3
Tads
––– Figure 3-4
Address/data hold time
3
Tadh
––– Figure 3-4