Datasheet

56F805 Technical Data, Rev. 16
24 Freescale Semiconductor
Figure 3-1 Maximum Run IDD vs. Frequency (see Note 6. in Figure 3-14)
3.3 AC Electrical Characteristics
Timing waveforms in Section 3.3 are tested using the V
IL
and V
IH
levels specified in the DC Characteristics
table. In Figure 3-2 the levels of V
IH
and V
IL
for an input signal are shown.
Figure 3-2 Input Signal Measurement References
Figure 3-3 shows the definitions of the following signal states:
• Active state, when a bus or signal is driven, and enters a low impedance state
• Tri-stated, when a bus or signal is placed in a high impedance state
• Data Valid state, when a signal level has reached V
OL
or V
OH
• Data Invalid state, when a signal level is in transition between V
OL
and V
OH
0
30
90
120
180
60
20
40
60
80
Freq. (MHz)
IDD (mA)
150
IDD Digital
IDD Analog
IDD Total
V
IH
V
IL
Fall Time
Input Signal
Note: The midpoint is V
IL
+ (V
IH
– V
IL
)/2.
Midpoint1
Low High
90%
50%
10%
Rise Time