Datasheet
Table Of Contents
- Part 1 Overview
- Part 2 Signal/Connection Descriptions
- 2.1 Introduction
- 2.2 Power and Ground Signals
- 2.3 Clock and Phase Locked Loop Signals
- 2.4 Address, Data, and Bus Control Signals
- 2.5 Interrupt and Program Control Signals
- 2.6 GPIO Signals
- 2.7 Pulse Width Modulator (PWM) Signals
- 2.8 Serial Peripheral Interface (SPI) Signals
- 2.9 Quadrature Decoder Signals
- 2.10 Serial Communications Interface (SCI) Signals
- 2.11 CAN Signals
- 2.12 Analog-to-Digital Converter (ADC) Signals
- 2.13 Quad Timer Module Signals
- 2.14 JTAG/OnCE
- Part 3 Specifications
- 3.1 General Characteristics
- 3.2 DC Electrical Characteristics
- 3.3 AC Electrical Characteristics
- 3.4 Flash Memory Characteristics
- 3.5 External Clock Operation
- 3.6 External Bus Asynchronous Timing
- 3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
- 3.8 Serial Peripheral Interface (SPI) Timing
- 3.9 Quad Timer Timing
- 3.10 Quadrature Decoder Timing
- 3.11 Serial Communication Interface (SCI) Timing
- 3.12 Analog-to-Digital Converter (ADC) Characteristics
- 3.13 Controller Area Network (CAN) Timing
- 3.14 JTAG Timing
- Part 4 Packaging
- Part 5 Design Considerations
- Part 6 Ordering Information
DC Electrical Characteristics
56F805 Technical Data, Rev. 16
Freescale Semiconductor 23
Output Low Voltage (at IOL) V
OL
——0.4V
Output source current I
OH
4——mA
Output sink current I
OL
4——mA
PWM pin output source current
3
I
OHP
10 — — mA
PWM pin output sink current
4
I
OLP
16 — — mA
Input capacitance C
IN
—8—pF
Output capacitance C
OUT
—12—pF
V
DD
supply current
I
DDT
5
Run
6
— 126 152 mA
Wait
7
— 105 129 mA
Stop —6084mA
Low Voltage Interrupt, external power supply
8
V
EIO
2.4 2.7 3.0 V
Low Voltage Interrupt, internal power supply
9
V
EIC
2.0 2.2 2.4 V
Power on Reset
10
V
POR
—1.72.0V
1. Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, ISA0-2, FAULTA0-3, ISB0-2, FAULT0B-3, TCS, TCK, TRST, TMS,
TDI, and MSCAN_RX
2. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.
3. PWM pin output source current measured with 50% duty cycle.
4. PWM pin output sink current measured with 50% duty cycle.
5. I
DDT
= I
DD
+ I
DDA
(Total supply current for V
DD
+ V
DDA
)
6. Run (operating) I
DD
measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as inputs;
measured with all modules enabled.
7. Wait I
DD
measured using external square wave clock source (f
osc
= 8MHz) into XTAL; all inputs 0.2V from rail; no DC loads; less
than 50pF on all outputs. C
L
= 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait I
DD
; measured
with PLL enabled.
8. This low voltage interrupt monitors the V
DDA
external power supply. V
DDA
is generally connected to the same potential as V
DD
via separate traces. If V
DDA
drops below V
EIO
, an interrupt is generated. Functionality of the device is guaranteed under transient
conditions when V
DDA
>V
EIO
(between the minimum specified V
DD
and the point when the V
EIO
interrupt is generated).
9. This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is regulator
drops below V
EIC
, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not be generated
unless the external power supply drops below the minimum specified value (3.0V).
10. Power–on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is ramping
up, this signal remains active as long as the internal 2.5V is below 1.5V typical, no matter how long the ramp-up rate is. The internally
regulated voltage is typically 100mV less than V
DD
during ramp-up until 2.5V is reached, at which time it self-regulates.
Table 3-4 DC Electrical Characteristics (Continued)
Operating Conditions: V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40° to +85°C, C
L
≤ 50pF, f
op
= 80MHz
Characteristic Symbol Min Typ Max Unit