Datasheet
Table Of Contents
- Part 1 Overview
- Part 2 Signal/Connection Descriptions
- 2.1 Introduction
- 2.2 Power and Ground Signals
- 2.3 Clock and Phase Locked Loop Signals
- 2.4 Address, Data, and Bus Control Signals
- 2.5 Interrupt and Program Control Signals
- 2.6 GPIO Signals
- 2.7 Pulse Width Modulator (PWM) Signals
- 2.8 Serial Peripheral Interface (SPI) Signals
- 2.9 Quadrature Decoder Signals
- 2.10 Serial Communications Interface (SCI) Signals
- 2.11 CAN Signals
- 2.12 Analog-to-Digital Converter (ADC) Signals
- 2.13 Quad Timer Module Signals
- 2.14 JTAG/OnCE
- Part 3 Specifications
- 3.1 General Characteristics
- 3.2 DC Electrical Characteristics
- 3.3 AC Electrical Characteristics
- 3.4 Flash Memory Characteristics
- 3.5 External Clock Operation
- 3.6 External Bus Asynchronous Timing
- 3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
- 3.8 Serial Peripheral Interface (SPI) Timing
- 3.9 Quad Timer Timing
- 3.10 Quadrature Decoder Timing
- 3.11 Serial Communication Interface (SCI) Timing
- 3.12 Analog-to-Digital Converter (ADC) Characteristics
- 3.13 Controller Area Network (CAN) Timing
- 3.14 JTAG Timing
- Part 4 Packaging
- Part 5 Design Considerations
- Part 6 Ordering Information
56F805 Technical Data, Rev. 16
20 Freescale Semiconductor
normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in Table 3-1 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
The 56F805 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.
CAUTION
This device contains protective circuitry to guard against damage due
to high static voltage or electrical fields. However, normal precautions
are advised to avoid application of any voltages higher than maximum
rated voltages to this high-impedance circuit. Reliability of operation
is enhanced if unused inputs are tied to an appropriate voltage level.
Table 3-1 Absolute Maximum Ratings
Characteristic Symbol Min Max Unit
Supply voltage V
DD
V
SS
– 0.3 V
SS
+ 4.0 V
All other input voltages, excluding Analog inputs, EXTAL
and XTAL
V
IN
V
SS
– 0.3 V
SS
+ 5.5V V
Voltage difference V
DD
to V
DDA
ΔV
DD
- 0.3 0.3 V
Voltage difference V
SS
to V
SSA
ΔV
SS
- 0.3 0.3 V
Analog inputs, ANA0-7 and VREF V
IN
V
SSA
– 0.3 V
DDA
+ 0.3 V
Analog inputs EXTAL and XTAL V
IN
V
SSA
– 0.3 V
SSA
+ 3.0 V
Current drain per pin excluding V
DD
, V
SS
, PWM outputs,
TCS, V
PP
, V
DDA
, V
SSA
I—10mA
Table 3-2 Recommended Operating Conditions
Characteristic Symbol Min Typ Max Unit
Supply voltage, digital V
DD
3.0 3.3 3.6 V
Supply Voltage, analog V
DDA
3.0 3.3 3.6 V