Datasheet
Table Of Contents
- Part 1 Overview
- Part 2 Signal/Connection Descriptions
- 2.1 Introduction
- 2.2 Power and Ground Signals
- 2.3 Clock and Phase Locked Loop Signals
- 2.4 Address, Data, and Bus Control Signals
- 2.5 Interrupt and Program Control Signals
- 2.6 GPIO Signals
- 2.7 Pulse Width Modulator (PWM) Signals
- 2.8 Serial Peripheral Interface (SPI) Signals
- 2.9 Quadrature Decoder Signals
- 2.10 Serial Communications Interface (SCI) Signals
- 2.11 CAN Signals
- 2.12 Analog-to-Digital Converter (ADC) Signals
- 2.13 Quad Timer Module Signals
- 2.14 JTAG/OnCE
- Part 3 Specifications
- 3.1 General Characteristics
- 3.2 DC Electrical Characteristics
- 3.3 AC Electrical Characteristics
- 3.4 Flash Memory Characteristics
- 3.5 External Clock Operation
- 3.6 External Bus Asynchronous Timing
- 3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
- 3.8 Serial Peripheral Interface (SPI) Timing
- 3.9 Quad Timer Timing
- 3.10 Quadrature Decoder Timing
- 3.11 Serial Communication Interface (SCI) Timing
- 3.12 Analog-to-Digital Converter (ADC) Characteristics
- 3.13 Controller Area Network (CAN) Timing
- 3.14 JTAG Timing
- Part 4 Packaging
- Part 5 Design Considerations
- Part 6 Ordering Information

Interrupt and Program Control Signals
56F805 Technical Data, Rev. 16
Freescale Semiconductor 13
2.5 Interrupt and Program Control Signals
Table 2-9 Interrupt and Program Control Signals
No. of
Pins
Signal
Name
Signal
Type
State
During
Reset
Signal Description
1 IRQA
Input
(Schmitt)
Input External Interrupt Request A—The IRQA input is a synchronized
external interrupt request indicating an external device is requesting
service. It can be programmed to be level-sensitive or
negative-edge-triggered.
1 IRQB Input
(Schmitt)
Input External Interrupt Request B—The IRQB input is an external
interrupt request indicating an external device is requesting service.
It can be programmed to be level-sensitive or
negative-edge-triggered.
1 RESET
Input
(Schmitt)
Input Reset—This input is a direct hardware reset on the processor.
When RESET is asserted low, the device is initialized and placed in
the Reset state. A Schmitt trigger input is used for noise immunity.
When the RESET
pin is deasserted, the initial chip operating mode
is latched from the EXTBOOT pin. The internal reset signal will be
deasserted synchronous with the internal clocks, after a fixed
number of internal clocks.
To ensure complete hardware reset, RESET
and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert
RESET
, but do not assert TRST.
1 RSTO
Output Output Reset Output—This output reflects the internal reset state of the
chip.
1 EXTBOOT Input
(Schmitt)
Input External Boot—This input is tied to V
DD
to force device to boot
from off-chip memory. Otherwise, it is tied to V
SS
.