Datasheet

56F803 Technical Data, Rev. 16
44 Freescale Semiconductor
1. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)
3. Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)
4. Sampling capacitor at the sample and hold circuit. (1pf)
Figure 3-26 Equivalent Analog Input Circuit
3.13 Controller Area Network (CAN) Timing
ADC Quiescent Current (both ADCs) I
ADC
—50 — mA
V
REF
Quiescent Current (both ADCs) I
VREF
—12 16.5 mA
1. For optimum ADC performance, keep the minimum V
ADCIN
value > 25mV. Inputs less than 25mV may convert to a digital
output code of 0.
2. V
REF
must be equal to or less than V
DDA
and must be greater than 2.7V. For optimal ADC performance, set V
REF
to V
D-
DA
-0.3V.
3. Measured in 10-90% range.
4. LSB = Least Significant Bit.
5. Guaranteed by characterization.
6. t
AIC
= 1/f
ADIC
Table 3-17 CAN Timing
2
Operating Conditions: V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40× to +85×C, C
L
£ 50pF, MSCAN Clock = 30MHz
Characteristic Symbol Min Max Unit
Baud Rate BR
CAN
—1Mbps
Bus Wakeup detection
1
T
WAKEUP
5—μs
Table 3-16 ADC Characteristics
Characteristic Symbol Min Typ Max Unit
1
2
3
4
ADC analog input