Datasheet

56F803 Technical Data, Rev. 16
40 Freescale Semiconductor
Figure 3-21 SPI Slave Timing (CPHA = 1)
3.9 Quad Timer Timing
Table 3-13 Timer Timing
1, 2
Operating Conditions: V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6V, T
A
= –40° to +85°C, C
L
≤ 50pF, f
OP
= 80MHz
Characteristic Symbol Min Max Unit
Timer input period P
IN
4T+6 — ns
Timer input high/low period P
INHL
2T+3 — ns
Timer output period P
OUT
2T — ns
SCLK (CPOL = 0)
(Input)
SCLK (CPOL = 1)
(Input)
MISO
(Output)
MOSI
(Input)
Slave MSB out Bits 14–1
MSB in Bits 14–1 LSB in
SS
(Input)
Slave LSB out
t
C
t
CL
t
DV
t
A
t
ELD
t
R
t
F
t
ELG
t
CH
t
CL
t
CH
t
F
t
DS
t
DV
t
DI
t
DH
t
D
t
R