Datasheet

Serial Peripheral Interface (SPI) Timing
56F803 Technical Data, Rev. 16
Freescale Semiconductor 37
Figure 3-18 SPI Master Timing (CPHA = 0)
Data Valid for outputs
Master
Slave (after enable edge)
t
DV
—
—
4.5
20.4
ns
ns
Figures 3-18, ,
3-20, 3-21
Data invalid
Master
Slave
t
DI
0
0
—
—
ns
ns
Figures 3-18, ,
3-20, 3-21
Rise time
Master
Slave
t
R
—
—
11.5
10.0
ns
ns
Figures 3-18, ,
3-20, 3-21
Fall time
Master
Slave
t
F
—
—
9.7
9.0
ns
ns
Figures 3-18, ,
3-20, 3-21
1. Parameters listed are guaranteed by design.
Table 3-12 SPI Timing
1
Operating Conditions: V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6V, T
A
= –40° to +85°C, C
L
≤ 50pF, f
OP
= 80MHz
Characteristic Symbol Min Max Unit See Figure
SCLK (CPOL = 0)
(Output)
SCLK (CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output)
MSB in Bits 14–1 LSB in
Master MSB out Bits 14–1 Master LSB out
SS
(Input)
SS is held High on master
t
R
t
F
t
F
t
DI
t
DS
t
DI
(ref)
t
DV
t
CH
t
DH
t
C
t
R
t
F
t
R
t
CL
t
CH
t
CL