Datasheet

56F803 Technical Data, Rev. 16
36 Freescale Semiconductor
Figure 3-17 Recovery from Stop State Using IRQA Interrupt Service
3.8 Serial Peripheral Interface (SPI) Timing
Table 3-12 SPI Timing
1
Operating Conditions: V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6V, T
A
= –40° to +85°C, C
L
≤ 50pF, f
OP
= 80MHz
Characteristic Symbol Min Max Unit See Figure
Cycle time
Master
Slave
t
C
50
25
—
—
ns
ns
Figures 3-18, ,
3-20, 3-21
Enable lead time
Master
Slave
t
ELD
—
25
—
—
ns
ns
Figure 3-21
Enable lag time
Master
Slave
t
ELG
—
100
—
—
ns
ns
Figure 3-21
Clock (SCLK) high time
Master
Slave
t
CH
17.6
12.5
—
—
ns
ns
Figures 3-18, ,
3-20, 3-21
Clock (SCLK) low time
Master
Slave
t
CL
24.1
25
—
—
ns
ns
Figures 3-18, ,
3-20, 3-21
Data set-up time required for inputs
Master
Slave
t
DS
20
0
—
—
ns
ns
Figures 3-18, ,
3-20, 3-21
Data hold time required for inputs
Master
Slave
t
DH
0
2
—
—
ns
ns
Figures 3-18, ,
3-20, 3-21
Access time (time to data active from high-impedance
state)
Slave
t
A
4.8 15 ns
Figure 3-21
Disable time (hold time to high-impedance state)
Slave
t
D
3.7 15.2 ns
Figure 3-21
Instruction Fetch
IRQA
A0–A15
PS
, DS,
RD
, WR
First IRQA Interrupt
t
IRQ
t
II