Datasheet

External Bus Asynchronous Timing
56F803 Technical Data, Rev. 16
Freescale Semiconductor 31
Input Data Hold to RD Deasserted t
DRD
0—ns
RD
Assertion Width
Wait states = 0
Wait states > 0
t
RD
19
(T*WS) + 19
—
—
ns
ns
Address Valid to Input Data Valid
Wait states = 0
Wait states > 0
t
AD
—
—
1
(T*WS) + 1
ns
ns
Address Valid to RD
Asserted t
ARDA
-4.4 — ns
RD
Asserted to Input Data Valid
Wait states = 0
Wait states > 0
t
RDD
—
—
2.4
(T*WS) + 2.4
ns
ns
WR
Deasserted to RD Asserted t
WRRD
6.8 — ns
RD
Deasserted to RD Asserted t
RDRD
0—ns
WR
Deasserted to WR Asserted t
WRWR
14.1 — ns
RD
Deasserted to WR Asserted t
RDWR
12.8 — ns
Table 3-10 External Bus Asynchronous Timing
1, 2
(Continued)
Operating Conditions: V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40° to +85°C, C
L
≤ 50pF, f
op
= 80MHz
Characteristic Symbol
Min
Max
Unit