Datasheet

56F803 Technical Data, Rev. 16
30 Freescale Semiconductor
3.5.4 Phase Locked Loop Timing
3.6 External Bus Asynchronous Timing
Table 3-9 PLL Timing
Operating Conditions: V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40° to +85°C
Characteristic Symbol Min Typ Max Unit
External reference crystal frequency for the PLL
1
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
2. ZCLK may not exceed 80MHz. For additional information on ZCLK and f
out
/2, please refer to the OCCS chapter in the
User Manual. ZCLK = f
op
3. This is the minimum time required after the PLL set-up is changed to ensure reliable operation.
f
osc
4810MHz
PLL output frequency
2
f
out
/2 40 — 110 MHz
PLL stabilization time
3
0
o
to +85
o
C
t
plls
—110ms
PLL stabilization time
3
-40
o
to 0
o
C
t
plls
— 100 200 ms
Table 3-10 External Bus Asynchronous Timing
1, 2
Operating Conditions: V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40° to +85°C, C
L
≤ 50pF, f
op
= 80MHz
Characteristic Symbol
Min
Max
Unit
Address Valid to WR Asserted t
AWR
6.5 — ns
WR
Width Asserted
Wait states = 0
Wait states > 0
t
WR
7.5
(T*WS) + 7.5
—
—
ns
ns
WR
Asserted to D0–D15 Out Valid t
WRD
—4.2ns
Data Out Hold Time from WR
Deasserted t
DOH
4.8 — ns
Data Out Set Up Time to WR
Deasserted
Wait states = 0
Wait states > 0
t
DOS
2.2
(T*WS) + 6.4
—
—
ns
ns
RD
Deasserted to Address Not Valid t
RDA
0—ns
Address Valid to RD
Deasserted
Wait states = 0
Wait states > 0
t
ARDD
18.7
(T*WS) + 18.7
—
ns
ns