Datasheet

56F801 Technical Data, Rev. 17
8 Freescale Semiconductor
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F801 are organized into functional groups, as shown in Table 2-1
and as illustrated in Figure 2-1. In Table 2-2 through Table 2-12, each table row describes the signal or
signals present on a pin.
Table 2-1 Functional Group Pin Allocations
Functional Group
Number of
Pins
Detailed
Description
Power (V
DD
or V
DDA
)5Table 2-2
Ground (V
SS
or V
SSA
)6Table 2-3
Supply Capacitors 2 Table 2-4
PLL and Clock 2 Table 2-5
Interrupt and Program Control 2 Table 2-6
Pulse Width Modulator (PWM) Port 7 Table 2-7
Serial Peripheral Interface (SPI) Port
1
1. Alternately, GPIO pins
4 Table 2-8
Serial Communications Interface (SCI) Port
1
2 Table 2-9
Analog-to-Digital Converter (ADC) Port 9 Table 2-10
Quad Timer Module Port 3 Table 2-11
JTAG/On-Chip Emulation (OnCE) 6 Table 2-12