Datasheet

JTAG Timing
56F801 Technical Data, Rev. 17
Freescale Semiconductor 39
Figure 3-28 Test Access Port Timing Diagram
Figure 3-29 TRST Timing Diagram
Figure 3-30 OnCE—Debug Event
Input Data Valid
Output Data Valid
Output Data Valid
TCK
(Input)
TDI
(Input)
TDO
(Output)
TDO
(Output
)
TDO
(Output)
TMS
t
DV
t
DV
t
TS
t
DS
t
DH
TRST
(Input)
t
TRST
DE
t
DE