Datasheet

56F801 Technical Data, Rev. 17
38 Freescale Semiconductor
3.11 JTAG Timing
Figure 3-27 Test Clock Input Timing Diagram
Table 3-16 JTAG Timing
1, 3
Operating Conditions: V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40° to +85°C, C
L
≤ 50pF
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz
operation, T = 12.5ns.
Characteristic Symbol Min Max Unit
TCK frequency of operation
2
2. TCK frequency of operation must be less than 1/8 the processor rate.
3. Parameters listed are guaranteed by design.
f
OP
DC 10 MHz
TCK cycle time t
CY
100 — ns
TCK clock pulse width t
PW
50 — ns
TMS, TDI data setup time t
DS
0.4 — ns
TMS, TDI data hold time t
DH
1.2 — ns
TCK low to TDO data valid t
DV
— 26.6 ns
TCK low to TDO tri-state t
TS
— 23.5 ns
TRST
assertion time t
TRST
50 — ns
DE
assertion time t
DE
8T — ns
TCK
(Input)
V
M
V
IL
V
M
= V
IL
+ (V
IH
– V
IL
)/2
V
M
V
IH
t
PW
t
PW
t
CY