Datasheet

56F801 Technical Data, Rev. 17
34 Freescale Semiconductor
Figure 3-21 SPI Slave Timing (CPHA = 0)
Figure 3-22 SPI Slave Timing (CPHA = 1)
SCLK (CPOL = 0)
(Input)
SCLK (CPOL = 1)
(Input)
MISO
(Output)
MOSI
(Input)
Slave MSB out Bits 14–1
MSB in Bits 14–1 LSB in
SS
(Input)
Slave LSB out
t
C
t
CL
t
F
t
ELG
t
R
t
DS
t
ELD
t
CH
t
CL
t
A
t
CH
t
R
t
F
t
D
t
DI
t
DV
t
DH
t
DI
SCLK (CPOL = 0)
(Input)
SCLK (CPOL = 1)
(Input)
MISO
(Output)
MOSI
(Input)
Slave MSB out Bits 14–1
MSB in Bits 14–1 LSB in
SS
(Input)
Slave LSB out
t
DI
t
D
t
R
t
DV
t
DH
t
F
t
DS
t
ELG
t
F
t
R
t
CH
t
DV
t
A
t
ELD
t
CL
t
CL
t
CH
t
C