Datasheet

Serial Peripheral Interface (SPI) Timing
56F801 Technical Data, Rev. 17
Freescale Semiconductor 33
Figure 3-19 SPI Master Timing (CPHA = 0)
Figure 3-20 SPI Master Timing (CPHA = 1)
SCLK (CPOL = 0)
(Output)
SCLK (CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output)
MSB in Bits 14–1 LSB in
Master MSB out Bits 14–1 Master LSB out
SS
(Input)
SS is held High on master
t
F
t
R
t
DI
(ref)
t
DV
t
DI
t
DS
t
DH
t
CH
t
CL
t
CH
t
F
t
F
t
R
t
R
t
CL
t
C
SCLK (CPOL = 0)
(Output)
SCLK (CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output)
MSB in Bits 14–1 LSB in
Master MSB out Bits 14– 1 Master LSB out
SS
(Input)
SS is held High on master
t
C
t
CL
t
CL
t
CH
t
CH
t
F
t
F
t
R
t
R
t
DS
t
DH
t
DV
t
DI
t
R
t
F
t
DV
(ref)