Datasheet

56F801 Technical Data, Rev. 17
32 Freescale Semiconductor
3.7 Serial Peripheral Interface (SPI) Timing
Table 3-12 SPI Timing
1
Operating Conditions: V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40° to +85°C, C
L
≤ 50pF
1. Parameters listed are guaranteed by design.
Characteristic Symbol Min Max Unit See Figure
Cycle time
Master
Slave
t
C
50
25
—
—
ns
ns
Figures 3-19, 3-20,
3-21, 3-22
Enable lead time
Master
Slave
t
ELD
—
25
—
—
ns
ns
Figure 3-22
Enable lag time
Master
Slave
t
ELG
—
100
—
—
ns
ns
Figure 3-22
Clock (SCK) high time
Master
Slave
t
CH
17.6
12.5
—
—
ns
ns
Figures 3-19, 3-20,
3-21, 3-22
Clock (SCK) low time
Master
Slave
t
CL
24.1
25
—
—
ns
ns
Figures 3-19, 3-20,
3-21, 3-22
Data setup time required for inputs
Master
Slave
t
DS
20
0
—
—
ns
ns
Figures 3-19, 3-20,
3-21, 3-22
Data hold time required for inputs
Master
Slave
t
DH
0
2
—
—
ns
ns
Figures 3-19, 3-20,
3-21, 3-22
Access time (time to data active from
high-impedance state)
Slave
t
A
4.8 15 ns
Figure 3-22
Disable time (hold time to high-impedance state)
Slave
t
D
3.7 15.2 ns
Figure 3-22
Data Valid for outputs
Master
Slave (after enable edge)
t
DV
—
—
4.5
20.4
ns
ns
Figures 3-19, 3-20,
3-21, 3-22
Data invalid
Master
Slave
t
DI
0
0
—
—
ns
ns
Figures 3-19, 3-20,
3-21, 3-22
Rise time
Master
Slave
t
R
—
—
11.5
10.0
ns
ns
Figures 3-19, 3-20,
3-21, 3-22
Fall time
Master
Slave
t
F
—
—
9.7
9.0
ns
ns
Figures 3-19, 3-20,
3-21, 3-22