Datasheet

56F801 Technical Data, Rev. 17
30 Freescale Semiconductor
Figure 3-13 Asynchronous Reset Timing
Figure 3-14 External Interrupt Timing (Negative-Edge-Sensitive)
Figure 3-15 External Level-Sensitive Interrupt Timing
First Fetch
A0–A15,
D0–D15
PS
, DS,
RD
, WR
RESET
First Fetch
t
RAZ
t
RA
t
RDA
IRQA,
IRQB
t
IRW
A0–A15,
PS, DS,
RD, WR
IRQA,
IRQB
First Interrupt Instruction Execution
a) First Interrupt Instruction Execution
General
Purpose
I/O Pin
IRQA,
IRQB
b) General Purpose I/O
t
IDM
t
IG