Datasheet

56F801 Technical Data, Rev. 17
28 Freescale Semiconductor
3.5.5 Phase Locked Loop Timing
Table 3-10 PLL Timing
Operating Conditions: V
SS
= V
SSA
= 0 V, V
DD
= V
DDA
= 3.0–3.6 V, T
A
= –40° to +85°C
Characteristic Symbol Min Typ Max Unit
External reference crystal frequency for the PLL
1
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
2. ZCLK may not exceed 80MHz. For additional information on ZCLK and f
out
/2, please refer to the OCCS chapter in the
User Manual. ZCLK = f
op
3. Will not exceed 60MHz for the DSP56F801FA60 device.
4. This is the minimum time required after the PLL setup is changed to ensure reliable operation.
f
osc
4810MHz
PLL output frequency
2
f
out
/2 40 —
80
3
MHz
PLL stabilization time
4
0
o
to +85
o
C
t
plls
—10—ms
PLL stabilization time
4
-40
o
to 0
o
C
t
plls
— 100 200 ms