Datasheet

NXP Semiconductors
QSG DAC1x08D+ECP3 DB
Quick Start Guide DAC1x08D + ECP3 demo board
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© NXP B.V. 2010. All rights reserved.
Quick Start Guide
Rev. 1.1 — 28 July 2010
3 of 17
1. Introduction
1.1 Demoboard overview:
Fig 1. Demo Board top view
NXP has designed a USB powered demo board to demonstrate the interoperability of
Lattice ECP3 FPGAs with NXP DAC over the JESD204A serial interface.
This board has 2 main modes of operation:
1. Using one single USB cable, it has to be configured so that only one DAC output
is active, in order to keep the power below the USB limit (500mA). This is
achieved thanks to the “1xDAC/2xDACs” jumper selector. At power-up, only the
DAC output A is active; it can be changed to DAC output B later on thanks to the
software running on a PC.
2. If the 2 outputs of the DAC (A & B) need to be used, it is necessary to properly
configure the “1xDAC/2xDACs” jumper selector and to connect a second USB
cable which is used for supply only.
In order to keep the demo set-up as simple as possible, an on-board 60MHz oscillator is
used to clock the FPGA, the JESD204A link and to drive the Sampling clock of the DAC.
It is also possible to use an external clock, to have more freedom and better jitter
performance. This is configured thanks to the Clock_Ext/Int jumper selector. It is adviced
to use the 2xDACs configuration (2 USB cables) when testing the external clock mode,
since the power consumption is rising when increasing the frequency and the USB limit
(500mA) might be crossed at high frequency.
The board has been successfully tested up to 200MHz. See Chapter 5 “5.Using an
external clock reference” for more details.
Clock In
Clock Out
DACA Out
DACB Out
Main USB
power USB
(2xDACs)
1xDAC/2xDACs
selector
Clock_Ext/Int
selector
Filter
Supplies ON
indicator
FPGA
DAC
USB2 required
indicator