Datasheet

DAC1405D750 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 31 January 2012 24 of 43
NXP Semiconductors
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating
10.4 Input clock
The DAC1405D750 can operate at the following clock frequencies:
PLL on: up to 185 MHz in Dual-port mode and up to 370 MHz in Interleaved mode
PLL off: up to 750 MHz
The input clock is LVDS compliant (see Figure 8
) but it can also be interfaced with CML
differential sine wave signal (see Figure 9
).
10.5 Timing
The DAC1405D750 can operate at a sampling frequency (f
s
) up to 750 Msps with an input
data rate (f
data
) up to 185 MHz. When using the internal PLL, the input data is referenced
to the CLK signal. When the internal PLL is bypassed, the SYNC signal is used as a
reference. The input timing in the second case is shown in Figure 10
.
Fig 8. LVDS clock configuration
Fig 9. Interfacing CML to LVDS
001aah021
100 Ω
LVDS
CLKINP
CLKINN
LVDS
Z
diff
= 100 Ω
001aah020
55 Ω
55 Ω
1.1 kΩ
2.2 kΩ
100 nF
CML
100 nF
100 nF
CLKINP
LVDS
CLKINN
AGND
V
DDA(1V8)
1 kΩZ
diff
= 100 Ω