Datasheet

DAC1405D750 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 31 January 2012 22 of 43
NXP Semiconductors
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating
10.2.5 Recommended configuration
It is recommended that the following additional settings are used to obtain optimum
performance at up to 750 Msps.
10.3 Input data
The setting applied to MODE_SEL (register 00h[3]; see Table 10 on page 17) defines
whether the DAC1405D750 operates in the Dual-port mode or in Interleaved mode (see
Table 32
).
10.3.1 Dual-port mode
The data input for Dual-port mode operation is shown in Figure 5 “Dual-port mode”. Each
DAC has its own independent data input. The data enters the input latch on the rising
edge of the internal clock signal and is transferred to the DAC latch.
Table 31. Recommended configuration
Address Value
Dec Hex Bin Dec Hex
17 11h 00001010 10 0Ah
19 13h 01101100 108 6Ch
20 14h 01101100 108 6Ch
Table 32. Mode selection
Bit 3 setting Function I13 to I0 Q13 to Q0 Pin 41
0 Dual port mode active active Q13
1 Interleaved mode active off SELIQ
Fig 5. Dual-port mode
001aal653
LATCH
I
2 × 2 × 2 ×
I13 to I0
FIR 1
FIR 1
FIR 2
FIR 2
FIR 3
FIR 3
LATCH
Q
2 × 2 × 2 ×
Q13 to Q0