Datasheet

DAC1405D750 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 31 January 2012 21 of 43
NXP Semiconductors
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating
Table 26. SYNC_Cfg register (address 10h) bit description
Default settings are shown highlighted.
Bit Symbol Access Value Description
7 SYNC_DIV R/W f
s
divided by
04
18
6 SYNC_SEL R/W SYNC selection
0disabled
1 enabled
5 to 0 - - - reserved
Table 27. DAC_A_Aux_MSB register (address 1Ah) bit description
Bit Symbol Access Value Description
7 to 0 AUX_A[9:2] R/W - most significant 8 bits for the auxiliary DAC A
Table 28. DAC_A_Aux_LSB register (address 1Bh) bit description
Default settings are shown highlighted.
Bit Symbol Access Value Description
7 AUX_A_PD R/W auxiliary DAC A power
0on
1off
6 to 1 - - - reserved
1 to 0 AUX_A[1:0] R/W lower 2 bits for the auxiliary DAC A
Table 29. DAC_B_Aux_MSB register (address 1Ch) bit description
Bit Symbol Access Value Description
7 to 0 AUX_B[9:2] R/W - most significant 8 bits for the auxiliary DAC B
Table 30. DAC_B_Aux_LSB register (address 1Dh) bit description
Default settings are shown highlighted.
Bit Symbol Access Value Description
7 AUX_B_PD R/W auxiliary DAC B power
0on
1off
6 to 1 - - - reserved
1 to 0 AUX_B[1:0] R/W lower 2-bits for the auxiliary DAC B