Datasheet

DAC1405D750 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 31 January 2012 20 of 43
NXP Semiconductors
DAC1405D750
Dual 14-bit DAC, up to 750 Msps; 4 and 8 interpolating
Table 21. DAC_A_Cfg_3 register (address 0Bh) bit description
Bit Symbol Access Value Description
7 to 6 DAC_A_GAIN_
COARSE[3:2]
R/W - most significant 2 bits for the DAC A gain
setting for coarse adjustment
5 to 0 DAC_A_
OFFSET[11:6]
R/W - most significant 6 bits for the DAC A offset
Table 22. DAC_B_Cfg_1 register (address 0Ch) bit description
Default settings are shown highlighted.
Bit Symbol Access Value Description
7 DAC_B_PD R/W DAC B power
0on
1off
6 DAC_B_SLEEP R/W DAC B Sleep mode
0disabled
1 enabled
5 to 0 DAC_B_OFFSET[5:0] R/W - lower 6 bits for the DAC B offset
Table 23. DAC_B_Cfg_2 register (address 0Dh) bit description
Bit Symbol Access Value Description
7 to 6 DAC_B_GAIN_
COARSE[1:0]
R/W - less significant 2 bits for the DAC B gain setting
for coarse adjustment
5 to 0 DAC_B_GAIN_
FINE[5:0]
R/W - the 6 bits for the DAC B gain setting for fine
adjustment
Table 24. DAC_B_Cfg_3 register (address 0Eh) bit description
Bit Symbol Access Value Description
7 to 6 DAC_B_GAIN_
COARSE[3:2]
R/W - most significant 2 bits for the DAC B gain
setting for coarse adjustment
5 to 0 DAC_B_
OFFSET[11:6]
R/W - most significant 6 bits for the DAC B offset
Table 25. DAC_Cfg register (address 0Fh) bit description
Default settings are shown highlighted.
Bit Symbol Access Value Description
7 to 2 - - - reserved
1 MINUS_3DB R/W NCO gain
0unity
1 3 dB
0 NOISE_SHPER R/W noise shaper
0 disabled
1 enabled